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| -_whitenotifier-f- [symbiflow-docs] tmeissner opened issue #292: VHDL-synthesis using GHDL as option in addition to verific - https://git.io/JfFWF | 18:32 | |
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| -_whitenotifier-f- [fpga-tool-perf] HackerFoo opened issue #165: Automate visualization of results - https://git.io/JfFRw | 20:45 | |
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| litghost | andrewb1999: Why would you need a synth IO with multiple IPINs or OPINs to support multiple clocks? | 22:15 |
|---|---|---|
| andrewb1999 | litghost: If I understand correctly, the nodes that I would want to connect a synth IO to for a clock all cross the roi at an hclk tile | 22:22 |
| andrewb1999 | And there is only one of those that could be used for each clock region | 22:23 |
| andrewb1999 | Maybe two | 22:23 |
| andrewb1999 | Is that incorrect? | 22:23 |
| litghost | You could stack the synth tiles using capacity | 22:24 |
| litghost | That enables the tiles at the same routing location, but enable multiple independent synth tiles | 22:24 |
| mithro | dkozel: Feel free to ask questions about what is needed to improve DSP support in this channel | 22:25 |
| mithro | dkozel: It's pretty much "all areas" from the bitstream documentation to the place and route support to the technology mapping in Yosys | 22:25 |
| andrewb1999 | litghost: That makes sense, trying manually now | 22:27 |
| mithro | andrewb1999: You should chat with dkozel -- He is from the Gnu Radio project and works on gr-verilog -- the gnu radio project could be an *awesome* target for things like Rosetta and the PR stuff... | 22:29 |
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