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| -_whitenotifier-3- [sv-tests] alainmarcel opened issue #701: Blackparrot bp_top test file list as an issue - https://git.io/Jviwn | 01:18 | |
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| yusef | Hello everyone, i want to get started with Gsoc projects on FPGA. how should i get started? | 10:21 |
|---|---|---|
| hackerfoo | yusef: https://summerofcode.withgoogle.com/organizations/6224851964002304/ https://github.com/SymbiFlow/ideas/issues | 10:33 |
| tpb | Title: Issues · SymbiFlow/ideas · GitHub (at github.com) | 10:33 |
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| yusef | and after selecting the ideas? | 11:21 |
| sf-slack | <pgielda> "Proposals accepted starting on March 16, 2020" -- so starting tomorrow its possible to apply | 11:24 |
| sf-slack | <pgielda> also read https://symbiflow.github.io/summer-of-code | 11:25 |
| tpb | Title: SymbiFlow - the GCC of FPGAs (at symbiflow.github.io) | 11:25 |
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| sf-slack | <yusef.iqbal44> thank you very much for your replies | 13:16 |
| sf-slack | <yusef.iqbal44> I was wondering to work on "Support Xilinx XC9500XL CPLD series" project... and I want to contribute to it | 13:22 |
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| ZirconiumX | yusef.iqbal44: I'm pretty sure that needs a copy of ISE | 13:27 |
| sf-slack | <yusef.iqbal44> xilinx ise? | 13:28 |
| ZirconiumX | Yep | 13:32 |
| ZirconiumX | Generally Vivado doesn't support any of their CPLDs | 13:32 |
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| sf-slack | <yusef.iqbal44> yup, you're damn right | 14:23 |
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| Guest15918 | Hi I have found that SymbiFlow has some interesting projects that I want to participate in kindly inform me where to start | 19:11 |
| ZirconiumX | Well, there's a github repo for it | 19:17 |
| ZirconiumX | Although you should pick a different nickname | 19:17 |
| ZirconiumX | https://github.com/Symbiflow/ideas/issues | 19:17 |
| tpb | Title: Issues · SymbiFlow/ideas · GitHub (at github.com) | 19:17 |
| ZirconiumX | That being said, there's a lot here that is missing | 19:18 |
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| Alaa501 | I have already red some of the projects written there and I found "Getting started with embedded RISC-V tutorial" as the most interesting. | 19:37 |
| ZirconiumX | I mean, ecosystem work is useful | 19:39 |
| ZirconiumX | Definitely not what I would have picked, but my opinion doesn't matter much | 19:39 |
| Alaa501 | I found it interesting thought .... what types of projects do you recommend working on | 19:42 |
| ZirconiumX | The main area I work on is a) Intel and b) Yosys | 19:46 |
| ZirconiumX | Because FOSS support for Intel chips is genuinely awful | 19:46 |
| ZirconiumX | But there are a bunch of things that Yosys could use | 19:47 |
| ZirconiumX | (IMO) | 19:47 |
| ZirconiumX | Mostly my focus is on LUT mapping | 19:50 |
| Alaa501 | interesting topics, however now I'm most interested about the FPGA's and RISC V and want to learn more about it. | 20:06 |
| Alaa501 | although I'm a beginner level but I'm willing to learn kindly provide any related learning materials if you know any | 20:06 |
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| ZirconiumX | Alaa501: Yosys is what produces a netlist for your FPGA; you're going nowhere without it :P | 20:40 |
| ZirconiumX | But for RISC-V you should study the instruction set manual if you haven't already | 20:41 |
| ZirconiumX | There's also #riscv | 20:41 |
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| wallacejohn | Hello, I am new here and have been lurking for a few days. I am interested in getting involved with this project. | 22:23 |
| wallacejohn | I found issue #1181 in vtr-verilog-to-routing and have converted my first script to Python 3 using 2to3 in my own fork. | 22:23 |
| wallacejohn | Should I go ahead and submit a pull request for this single script, or convert several scripts before submitting a pull request? | 22:24 |
| wallacejohn | This will be my first pull request, so I apologize for the basic question. Thanks! | 22:24 |
| ZirconiumX | I think all of them should be updated to Py3 honestly | 22:34 |
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