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| sf-slack | <garvit.gupta08> Hello everyone. I recently did my coursework in FPGA especially on artix7 basys3board ( xc7a35tcpg236-1) and I am comfortable with FPGA design and its components. I am also comfortable with verilog and C. I saw the project xray and found it exciting. A little help on additional resources which I can go through to start working on it as soon as possible. | 10:40 |
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| IRC-Source_51 | Greetings everyone ! | 12:48 |
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| ZirconiumX | Hello | 13:01 |
| IRC-Source_51 | how are you doing ? | 13:01 |
| ZirconiumX | Not too badly I guess | 13:01 |
| IRC-Source_51 | nice :) | 13:02 |
| IRC-Source_51 | I came here seeking some help with project Xray | 13:02 |
| IRC-Source_51 | could you help me with that ? | 13:02 |
| ZirconiumX | I don't have any experience there | 13:16 |
| ZirconiumX | Especially since my limited energies are focused on reverse engineering Intel chips | 13:16 |
| ZirconiumX | Not Xilinx | 13:16 |
| IRC-Source_51 | Oh I see, so you are working on a similar project for altera fpgas ? | 13:17 |
| ZirconiumX | Kinda? We're not nearly as far as X-Ray is | 13:18 |
| IRC-Source_51 | Thats very interesting :) | 13:18 |
| IRC-Source_51 | Are you following similar methodology/approach ? | 13:18 |
| ZirconiumX | Because I'm a student working on a lot of things | 13:19 |
| *** IRC-Source_51 is now known as Clay_1 | 13:19 | |
| ZirconiumX | I have a pretty different approach actually | 13:19 |
| Clay_1 | you are working alone there ? | 13:19 |
| ZirconiumX | You can't get nearly as low-level with Quartus as you can with Vivado | 13:20 |
| ZirconiumX | Not entirely. There are a few people who offer advice and one person who is trying to help | 13:20 |
| Clay_1 | i see, so what is your approach ? | 13:21 |
| ZirconiumX | I named it Project Mistral but it's less of a project and more of a hobby | 13:21 |
| Clay_1 | you have a repo ? | 13:22 |
| ZirconiumX | I do, but it's not up to date as such | 13:22 |
| Clay_1 | I see, nice :) | 13:23 |
| ZirconiumX | https://github.com/ZirconiumX/mistral | 13:24 |
| tpb | Title: GitHub - ZirconiumX/mistral: Cyclone V bitstream reverse-engineering project (at github.com) | 13:24 |
| ZirconiumX | (the Mistral is a strong wind that blows along the south-east of France, and I thought it'd be funny since I was targeting Cyclone chips) | 13:25 |
| Clay_1 | nice trail of though | 13:26 |
| Clay_1 | are cyclone vs similar to ivs ? | 13:26 |
| ZirconiumX | Very different | 13:26 |
| Clay_1 | i see | 13:27 |
| ZirconiumX | But the 10GX is a die-shrink of the V, the 10LP is a die-shrink of the IV, and the Max 10 is a die-shrink of the III | 13:27 |
| Clay_1 | so the V's would be the rough equivalent of 7series ? | 13:28 |
| ZirconiumX | Kinda yeah | 13:28 |
| Clay_1 | nice :) | 13:28 |
| ZirconiumX | The actual technology goes back way further though | 13:28 |
| ZirconiumX | The Arria II had ALMs like the Cyclone V | 13:28 |
| ZirconiumX | Much like the Virtex 5 had LUT6s | 13:29 |
| Clay_1 | I am totally clueless when it comes to altera boards | 13:30 |
| Clay_1 | I used quartus for the first time last week | 13:30 |
| Clay_1 | and I cant really say I liked it | 13:30 |
| Clay_1 | what is your reason of prefering altera over xilinx? | 13:30 |
| ZirconiumX | I use it from the command line so I don't have to bother with the GUI | 13:31 |
| ZirconiumX | I first bought an FPGA for the MiSTer project, which uses the Terasic DE-10 Nano | 13:31 |
| Clay_1 | that's tcl, right ? | 13:31 |
| ZirconiumX | Not necessarily | 13:31 |
| Clay_1 | you sound very knowledgeable on the subject :) | 13:32 |
| ZirconiumX | Anyway, after getting immensely frustrated at Quartus, I looked for alternatives and stumbled upon Yosys | 13:33 |
| ZirconiumX | And well, here I am | 13:33 |
| Clay_1 | That makes sense | 13:33 |
| ZirconiumX | When you're reverse-engineering an FPGA you need to know the architecture as much as possible | 13:33 |
| ZirconiumX | Or things don't make sense | 13:33 |
| ZirconiumX | The ALM is a LUT6 like the Xilinx (CLB?) | 13:34 |
| Clay_1 | indeed | 13:34 |
| ZirconiumX | But the internal architecture is very different | 13:34 |
| Clay_1 | xilinx has lut6 as part of a clb | 13:35 |
| ZirconiumX | Xilinx LUT6s look like two LUT5s with separate outputs that get multiplexed by a sixth input | 13:35 |
| ZirconiumX | So if you want to fit two LUT5s in a CLB they need to share all five terms | 13:36 |
| ZirconiumX | Or else you can have small independent functions like a LUT2 and a LUT3 with no shared terms or two LUT3s with a shared term | 13:36 |
| ZirconiumX | Altera ALMs look like four LUT4s which get multiplexed by two bits, but they have 8 inputs instead of 5+1 | 13:38 |
| Clay_1 | "Xilinx LUT6s look like two LUT5s with separate outputs that get multiplexed by a sixth input" yes I would agree with that | 13:38 |
| ZirconiumX | So you can implement two independent LUT4s in an ALM | 13:38 |
| Clay_1 | sounds more complex | 13:38 |
| ZirconiumX | https://puu.sh/FfHHu/ae30d04fca.png | 13:40 |
| Clay_1 | which are the logical lut inputs ? | 13:41 |
| ZirconiumX | It depends on the function being implemented | 13:44 |
| Clay_1 | you can have a max of 6 inputs, right ? | 13:44 |
| ZirconiumX | ...Kind of. You can implement *some* forms of a LUT7 in here | 13:44 |
| Clay_1 | wow | 13:45 |
| ZirconiumX | Unfortunately you need specialised techmapping to take advantage of it | 13:45 |
| Clay_1 | do you have full controll over that or the tool will decide ? | 13:45 |
| Clay_1 | oh ok | 13:45 |
| ZirconiumX | The synthesis tool handles it | 13:45 |
| Clay_1 | For Xilinx, I find the following paper very insightful of how luts work | 13:47 |
| Clay_1 | https://ieeexplore.ieee.org/document/8350950 | 13:47 |
| tpb | Title: Extract LUT Logics from a Downloaded Bitstream Data in FPGA - IEEE Conference Publication (at ieeexplore.ieee.org) | 13:47 |
| Clay_1 | you have access to ieeexplore, right ? | 13:47 |
| ZirconiumX | I probably will at uni | 13:48 |
| ZirconiumX | But it's a problem I've already solved | 13:48 |
| Clay_1 | the re of lut contents for quartus generated bitstreams ? | 13:48 |
| ZirconiumX | Yeah | 13:49 |
| Clay_1 | cool | 13:49 |
| Clay_1 | how did you do that ? | 13:49 |
| * ZirconiumX sighs | 13:49 | |
| Clay_1 | long story ? | 13:49 |
| ZirconiumX | I need to write a paper about it so I don't have to keep explaining to everyone | 13:49 |
| ZirconiumX | :P | 13:49 |
| Clay_1 | would be a good idea | 13:50 |
| Clay_1 | haha | 13:50 |
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| ZirconiumX | For any boolean feature, you assign a unique non-zero identifier to it, and when you have all the ones enumerated, you produce a series of bitstreams where the Nth bitstream has the Nth bit of the feature index | 13:51 |
| Clay_1 | the design of that bitstream is a single lut ? | 13:52 |
| ZirconiumX | "for any boolean feature" | 13:52 |
| ZirconiumX | So not just LUTs | 13:52 |
| ZirconiumX | For example, see the multiplexers feeding into the flip-flops? | 13:53 |
| Clay_1 | yes | 13:53 |
| ZirconiumX | Those are boolean features that could be tested | 13:53 |
| ZirconiumX | If you knew how to cause them | 13:53 |
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| Clay_1 | oh | 13:54 |
| Clay_1 | thats cool | 13:54 |
| Clay_1 | so you have done that for every such element ? | 13:56 |
| ZirconiumX | At the moment no; I wanted to focus on routing, but that turns out to be a pain that requires thought | 14:30 |
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| Adrofier | is anyone applying to gsoc this year? | 15:12 |
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| Clay_1 | ZirconiumX I see | 16:50 |
| Clay_1 | That's the part I would say that interests me the most in the xilinx part | 16:50 |
| Clay_1 | project x-ray seems to have solved this but I cant really understand their documentation :/ thus I came here to seek for help | 16:51 |
| ZirconiumX | I mean, you can use the approach I mentioned for basically anything | 16:53 |
| Clay_1 | well, technically, routing is already documented in project xray, isnt it ? | 16:58 |
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