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| -_whitenotifier-3- [prjxray] litghost opened issue #1258: Document remaining bits in opentitan bitstream - https://git.io/JvzKK | 00:18 | |
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| sf-slack | <shahbaazlokhandwala> Hi guys, i work as FPGA applications engineer, just recently got to know about symbiflow, excited to test and learn workflow. | 07:23 |
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| -_whitenotifier-3- [fpga-tool-perf] kgugala opened issue #51: Generate nicer reports - https://git.io/JvzQe | 08:47 | |
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| ZirconiumX | shahbaazlokhandwala: how much do you know about FPGA architecture? | 09:11 |
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| sf-slack | <ssamuel> Hi Everyone, I am an Electrical Engineer Graduate from IIT Roorkee. I have worked on many projects related to SDR and I am very comfortable with FPGA Design and well versed with C and Python. I am very excited to work on SymbiFlow and hope I could really help in the projects. | 11:53 |
| ZirconiumX | ssamuel: how much do you know about FPGA architecture? | 11:56 |
| ZirconiumX | For example, if I mentioned a LUT or DSP would you know what I'm talking about? | 11:58 |
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| sf-slack | <ssamuel> Hi, I am comfortable with FPGA Design, especially the ZynQ Architecture during my collage days I have worked with BRAMs, Filter Designs, FPGA-ARM data communication using AMBA and my college internship was to design a test-bed for GPS ASIC (who logic was to be tested) and I am also comfortable with Verilog and C. I am not that good with linux device drivers but I am working on it. :) | 12:18 |
| sf-slack | <ssamuel> Maybe a little brush-up and I am good to go :) | 12:18 |
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| ZirconiumX | ssamuel: I didn't ask about FPGA design; you probably won't be doing any here | 12:50 |
| ZirconiumX | I said architecture, as in how FPGAs work | 12:50 |
| ZirconiumX | Not how to write gateware on top of them | 12:50 |
| sf-slack | <ssamuel> Okay, Yes I know how FPGAs work | 12:53 |
| ZirconiumX | There is one main project I'd consider directly associated with Symbiflow: Project X-Ray | 12:54 |
| ZirconiumX | And a bunch of periphery projects which are run by Symbiotic EDA | 12:55 |
| sf-slack | <ssamuel> Okay | 12:56 |
| ZirconiumX | Given your experience with Xilinx and Zynq, I presume you want to add support for it to the FOSS FPGA flow | 12:59 |
| ZirconiumX | There are three main parts to it: synthesis, provided by Yosys, place and route, provided by *either* nextpnr or VPR, and bitstream tooling, provided by Project X-Ray | 13:02 |
| sf-slack | <ssamuel> Okay, I get it | 13:03 |
| ZirconiumX | So consider which one you want to work on | 13:03 |
| ZirconiumX | There is much that can be done to benefit the entire ecosystem as opposed to one specific target | 13:04 |
| ZirconiumX | But most of it is in Yosys | 13:04 |
| ZirconiumX | My personal opinion is that if you're going to work on place and route, pick nextpnr, not VPR | 13:05 |
| ZirconiumX | It is notably more modern and closer to the state of the art | 13:05 |
| ZirconiumX | Which results in faster placement and better quality routing | 13:06 |
| ZirconiumX | But I personally work on Yosys | 13:07 |
| ZirconiumX | And I have a few things that I could help with | 13:07 |
| ZirconiumX | In particular I think Yosys could benefit from a better LUT mapping system | 13:10 |
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| sf-slack | <ssamuel> Can I go through both Yosys and nextpnr and then I will let you know | 13:12 |
| ZirconiumX | Yosys is actually fairly readable I think | 13:17 |
| ZirconiumX | Haven't looked too much at nextpnr however | 13:17 |
| sf-slack | <ssamuel> I am interested in working on nextpnr :). | 13:43 |
| ZirconiumX | So, for Xilinx stuff there's nextpnr-xilinx which is run by daveshah | 13:46 |
| ZirconiumX | Which uses X-Ray for XC7 and RapidWright for XCU/XCUP | 13:46 |
| ZirconiumX | I personally am trying to RE the Intel Cyclone V (which I think will be helpful for the Cyclone 10GX) | 13:47 |
| ZirconiumX | But adding people to a late project with a bad leader makes things later >.> | 13:47 |
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| IRC-Source_63 | Hello! | 18:18 |
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| -_whitenotifier-3- [fasm] mithro opened issue #19: FASM readthedocs is broken - https://git.io/JvgOL | 22:52 | |
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