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| jjjaaaccckkk | fanyone have Mathias Lasser's full slide deck from his presentation at 34C3 about reverse engineering the xilinx series 7? | 01:26 |
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| az0re | jjjaaaccckkk: https://media.ccc.de/v/34c3-9237-reverse_engineering_fpgas doesn't work for you? | 02:19 |
| tpb | Title: media.ccc.de - Reverse engineering FPGAs (at media.ccc.de) | 02:19 |
| az0re | Ah, just saw your message in #yosys... sorry, can't help | 02:21 |
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| jjjaaaccckkk | no worries, yeah I was hoping someone has all the slides from his presentation. In the video he seemed glad to share them with whoever was interested | 02:28 |
| jjjaaaccckkk | Or anyone know Mathias and can ask if he is open to sharing them? | 02:30 |
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| * bunnie[m] sent a long message: < https://matrix.org/_matrix/media/r0/download/matrix.org/UIkSZnmdAnMMCUPdwkTgLwlA > | 15:13 | |
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| ZirconiumX | bunnie[m]: the Intel bitstream is even stranger | 15:44 |
| bunnie[m] | yow. | 15:58 |
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| mithro | jjjaaaccckkk: I attended and he didn't have any slides and pretty much no real details | 19:15 |
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| jjjaaaccckkk | Thanks, mithro | 21:06 |
| mithro | It is in no way connected to prjxray | 21:19 |
| jjjaaaccckkk | Yep I knew that | 21:28 |
| az0re | What is the difference between prjxray and his work? | 21:29 |
| mithro | az0re: his work doesn't exist as far as I can tell, prjxray is mostly just missing DSP + Serdes | 21:37 |
| az0re | Gotcha, thanks | 21:46 |
| mithro | prjxray is at https://github.com/SymbiFlow/prjxray and prjxray.rtfd.io | 21:49 |
| tpb | Title: GitHub - SymbiFlow/prjxray: Documenting the Xilinx 7-series bit-stream format. (at github.com) | 21:49 |
| jjjaaaccckkk | I am curious, though, do you understand the technique Mathias talked about? It sounds like he was implementing Vivado example projects and reading each pixel in the device view image to see what bits were set? | 22:25 |
| az0re | mithro: Cool work. Thanks for doing it! | 22:27 |
| az0re | I haven't really dug into it yet, but my impression is that the process is roughly like: | 22:27 |
| az0re | 1. Read documentation, get an idea of what resources exist on the FPGA family | 22:28 |
| mithro | jjjaaaccckkk: You generate a lot of bitstreams and then look for cross correlation between bits and features | 22:28 |
| mithro | jjjaaaccckkk: There is some info in the docs above | 22:28 |
| az0re | 2. Write fuzzer generator scripts to instantiate those IP features in uniquely identifiable ways | 22:28 |
| az0re | 3. Do the full design flow in the Xilinx tools, observe changes in the bitstream | 22:28 |
| az0re | 4. Correlate unique identifiers (or uniquely identifying behaviors?) with bits in the bitstream | 22:29 |
| az0re | Is that about right? | 22:29 |
| -_whitenotifier-5- [sphinx_materialdesign_theme] mithro opened issue #1: script_files in the theme is deprecated - https://git.io/JvfbR | 23:17 | |
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| mithro | az0re: pretty much | 23:43 |
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