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| hackerfoo | tmichalak: Do you have the source Migen used to generate https://github.com/SymbiFlow/prjxray/pull/1119? ZirconiumX in ##openfpga is interested in examples of how to use LiteDRAM. | 01:00 |
|---|---|---|
| tpb | Title: minitests: Add test for Litex DRAM memory interface by tmichalak · Pull Request #1119 · SymbiFlow/prjxray · GitHub (at github.com) | 01:00 |
| hackerfoo | Nevermind: https://github.com/antmicro/prjxray/tree/litex_litedram/minitests/litex | 01:10 |
| tpb | Title: prjxray/minitests/litex at litex_litedram · antmicro/prjxray · GitHub (at github.com) | 01:10 |
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| owlhawk | I managed to run the fuzzers with Vivado 2018.1. Had to take out a part of 005-tilegrid related to the BSCANE2 block, which was causing a DRC error that I couldn't figure out an easy workaround for. No other issues though. | 06:38 |
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| owlhawk | mithro: I never encountered the issue #14 related to MUXF8 that you pointed me to last week | 06:38 |
| owlhawk | Just started a run now with my first attempt at a spartan-7 configuration. Will see how that goes | 06:39 |
| sf-slack | <tmichalak> Hackerfoo: Does nevermind mean that the minitest you found is enough or do you still neede the Migen source for it? I will be doing more Litex minitests and will add the target Migen sources there. In this particular minitest there is only final verilog. | 06:43 |
| hackerfoo | It means I thought I found the source, but I think that's only for the full SoC. | 06:44 |
| sf-slack | <tmichalak> Yeah, that's the full SoC | 06:45 |
| hackerfoo | Do you have the source available? ZirconiumX was looking for an example of how to use LiteDRAM, and I thought the minitest might be a good one. | 06:47 |
| sf-slack | <tmichalak> For the whole SoC? Let me have a look. | 06:49 |
| hackerfoo | Wasn't there one for just the DDR controller? That's what I was looking for. | 06:53 |
| sf-slack | <tmichalak> No, we don't have such a test yet. We really need to have it working with the vexriscv so we kept the SoC for now. | 07:03 |
| hackerfoo | Okay, thanks. | 07:04 |
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| OmniMancer | what is the correct method to uninstall vivado on linux? | 08:41 |
| sf-slack | <kgugala> OmniMancer: simply remove the directory where it is installed? | 08:42 |
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| sf-slack | <acomodi> @litghost: I cannot push force on yosys fork to update `master` and `master+wip` but I have created two `wip/` with the outstanding difference w.r.t to master, there is also a `new-master-wip` branch that includes the wip branches | 11:09 |
| sf-slack | <acomodi> I think that we need an initial forced push to master+wip and than we can follow with the same strategy as for VtR with the integration points | 11:10 |
| lromor[m] | Hi! I wanted to write some documentation. Is it possible to publish screenshots of the vivado view of the fpga schematics or it's not allowed by xilinx? | 12:37 |
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| -_whitenotifier-e- [vtr-verilog-to-routing] litghost opened issue #333: Faster VPR rrgraph load - https://git.io/JeXwy | 21:02 | |
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| bunnie | Are there any bits in the bitstream that are "unknownable", as in, no amount of fuzzing has revealed their function to date? | 22:12 |
| bunnie | it looks like even the "undocumented" PHASER block is in the tilegrid, but is there a test or routine that checks for total bitstream coverage in case there are other blocks like that? | 22:18 |
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