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| mithro | litghost: It looks like there are changes to the fasm tool which hasn't been sent upstream to vtr? | 00:08 |
|---|---|---|
| litghost | mithro: 3 I believe now. The router changes, hackerfoo's parameter change and your pointer fix | 00:09 |
| mithro | litghost: I don't see any upstream pull requests for them? | 00:10 |
| litghost | mithro: I was waiting till the decision was made for genfasm sub-stuff | 00:10 |
| mithro | litghost: genfasm sub-stuff? | 00:10 |
| litghost | mithro: https://help.github.com/en/articles/about-code-owners | 00:11 |
| mithro | litghost: Oh you mean OWNERs | 00:11 |
| litghost | mithro: I forgot what it was called | 00:11 |
| mithro | I would just send it | 00:11 |
| mithro | litghost: Did you see that one of the fasm unittests is failing? | 00:50 |
| mithro | litghost: https://travis-ci.com/SymbiFlow/conda-packages/jobs/203734750#L4884 | 00:50 |
| tpb | Title: Travis CI - Test and Deploy with Confidence (at travis-ci.com) | 00:50 |
| mithro | litghost: also https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/610 | 00:51 |
| tpb | Title: Run unit tests in Travis CI · Issue #610 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 00:51 |
| mithro | litghost: Should I look at it? | 00:52 |
| litghost | mithro: Feel free | 00:52 |
| mithro | https://www.irccloud.com/pastebin/BP5j1huL/ | 00:53 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 00:53 |
| mithro | litghost: Should they have that newline? | 00:54 |
| litghost | Yes, ish | 00:54 |
| litghost | The answer is yes | 00:54 |
| litghost | it | 00:54 |
| litghost | should have the newline | 00:54 |
| litghost | The better answer is, the newline doesn't matter, so the test simply behaving like a change detector | 00:54 |
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| mithro | hackerfoo: When you get a moment, can you look at https://github.com/SymbiFlow/symbiflow-arch-defs/pull/779 ? | 04:22 |
| tpb | Title: xc7: Use the common_slice definition when LUTRAM used as a LUT. by mithro · Pull Request #779 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 04:22 |
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| sf-slack2 | <acomodi> litghost: I am dealing with the non-consecutive ptc. I have applied the changes here https://github.com/SymbiFlow/vtr-verilog-to-routing/pull/64 | 14:48 |
| tpb | Title: WIP: rr_graph_reader: allow non-consecutive ptc by acomodi · Pull Request #64 · SymbiFlow/vtr-verilog-to-routing · GitHub (at github.com) | 14:48 |
| sf-slack2 | <acomodi> litghost: I still need to find all the locations where I need to have a check whether the inode is valid or not | 14:49 |
| sf-slack2 | <acomodi> litghost: I have removed the dummy_tracks from the `routing_import.py` script and tested if now the routing reading happens correctly and it does. | 14:50 |
| sf-slack2 | <acomodi> litghost: the issue is that now router loops infinitely and the Overused RR nodes increase at each iteration | 14:50 |
| sf-slack2 | <mkurc> @litghost: I filed an issue to the VPR regarding modelling of async S/R flip-flops: https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/617 | 15:21 |
| tpb | Title: Problem defining a FF with async reset with timings · Issue #617 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 15:21 |
| sf-slack2 | <mkurc> @litghost And I got an answer which from my understanding means that such logic is currently not supported. | 15:22 |
| sf-slack2 | <mkurc> @litghost The functionality of such a FF does not correspond to any timing model shown in the examples: https://docs.verilogtorouting.org/en/latest/tutorials/arch/timing_modeling/#arch-model-timing-tutorial | 15:24 |
| sf-slack2 | <mkurc> @litghost I think that what we need is a cell model which has FFs on D and CE inputs but the output Q depends on those FFs plus on the CLR (combinationaly) | 15:27 |
| sf-slack2 | <mkurc> @litghost We need something like that: https://pasteboard.co/IgXtm7W.png | 15:30 |
| tpb | Title: Pasteboard - Uploaded Image (at pasteboard.co) | 15:30 |
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| litghost | One way to model that might be to emit two black boxes | 17:11 |
| litghost | Have the combitorial path from SR to Q in the second black box, and SR to CLK in the first second black box | 17:12 |
| litghost | Just an idea off the top of my head, unclear if that would actually work | 17:12 |
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| sf-slack2 | <kgugala> @mithro we really need the latest database to get green CI on this one https://github.com/SymbiFlow/symbiflow-arch-defs/pull/738 | 20:59 |
| tpb | Title: Arch XML timings by kgugala · Pull Request #738 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 20:59 |
| mithro | kgugala: Okay, will look at that this afternoon | 21:00 |
| sf-slack2 | <kgugala> awesome, thanks | 21:00 |
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| hackerfoo | I found this to descramble parallel make output: https://www.gnu.org/software/make/manual/html_node/Parallel-Output.html | 21:32 |
| tpb | Title: GNU make: Parallel Output (at www.gnu.org) | 21:32 |
| sf-slack2 | <kgugala> this is really cool | 21:35 |
| mithro | hackerfoo: Already tried that previously it doesn't really work in our system | 21:57 |
| mithro | hackerfoo: https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/.github/kokoro/ice40.sh#L15 | 21:57 |
| tpb | Title: symbiflow-arch-defs/ice40.sh at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 21:57 |
| hackerfoo | mithro: --output-sync=recurse also doesn't work? On local builds it seems to be better, at least. | 22:00 |
| mithro | hackerfoo: I think the issue is that it ends up with no output until the command finishes | 22:44 |
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| hackerfoo | Interleaving 36k bits seems to be a lot of work for Yosys. | 23:29 |
| litghost | hackerfoo: Like its slow? | 23:29 |
| litghost | hackerfoo: Or just hard to do? | 23:29 |
| hackerfoo | litghost: It's been running for a while now. | 23:35 |
| litghost | hackerfoo: Any chance you made an infinite loop? | 23:35 |
| litghost | hackerfoo: I'd bet on an infinite loop over Yosys being super slow, but who knows | 23:35 |
| * hackerfoo sent a long message: < http://sandbox.hackerfoo.com:8008/_matrix/media/v1/download/sandbox.hackerfoo.com/gbjHkWRcrlmCqDsAnXlasLGG > | 23:46 | |
| hackerfoo | litghost: ^ I don't think so? | 23:47 |
| litghost | hackerfoo: Depends on the width of i, but I assume it's a 32-bit int | 23:47 |
| litghost | hackerfoo: Might be worth making a little example and profile it | 23:48 |
| litghost | hackerfoo: something like interleave 1k, 2k, 4k, etc | 23:48 |
| mithro | hackerfoo: I think you want i to be an integer rather than a 1 bit width register? | 23:48 |
| litghost | hackerfoo: Oh, also you problably want to be using generate for and genvar? | 23:49 |
| hackerfoo | Can't generate in a function. | 23:49 |
| litghost | hackerfoo: Does it work without the function as a generate statement? | 23:50 |
| litghost | hackerfoo: Working is better than pretty | 23:50 |
| litghost | hackerfoo: Anyways, I think @mithro has the right idea, reg by itself isn't wide enough | 23:50 |
| litghost | hackerfoo: So you did make an infinite loop | 23:51 |
| hackerfoo | Sure. I'll keeping trying stuff until I find something that works. | 23:51 |
| mithro | hackerfoo: I 1bit register will never get bigger than 1, not matter how much you want it too :-P | 23:51 |
| hackerfoo | I was trying to use a 7-level macro, but couldn't figure that out. | 23:51 |
| mithro | I would think a generate statement would just work in this case? | 23:52 |
| litghost | 7-level? | 23:52 |
| hackerfoo | good catch litghost , but now it just seems to crash. | 23:52 |
| hackerfoo | 2^7 | 23:52 |
| litghost | Well crashing is a yosys bug you can file :) | 23:52 |
| hackerfoo | mithro: Depends on how much voltage you apply. | 23:52 |
| litghost | Or do you mean generating an error | 23:52 |
| hackerfoo | I can't find the error, at least. | 23:53 |
| litghost | hackerfoo: I recommend a nice small reproducible case, and create an issue upstream once you've narrowed it | 23:58 |
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