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| BryceSchroeder_ | Wow, what a pain in the butt it is to try to get the free lattice diamond license that was supposed to come with the eval board I bought | 01:12 |
|---|---|---|
| BryceSchroeder_ | it's a complete nightmare, it wouldn't recognize my company email, and when I tried to contact their support with gmail I got an automatic message saying it was being ignored because it was from gmail | 01:13 |
| BryceSchroeder_ | FOSS tools can't happen fast enough :/ | 01:13 |
| hedgeberg | yeah, tbh. | 02:29 |
| hedgeberg | like, foss fpga tools lack a lot of features and I'm still happy to use them over the pro tools | 02:29 |
| hedgeberg | its just completely unreasonable how bad the pro tool licensing and usability are. | 02:30 |
| zkms | the open source tools are pretty much the reason i actually was able to learn fpga things ;-; | 02:30 |
| BryceSchroeder_ | I think these companies are doing themselves a disservice since their tools only work with the ICs they sell | 02:33 |
| BryceSchroeder_ | really the tools should be free and they should just sell chips and IP cores, imho. | 02:34 |
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| digshadow | hey hedgeberg | 06:48 |
| digshadow | Let me know if you need anything to get started with prjxray | 06:48 |
| digshadow | noopwafel: were you able to make progress? | 06:52 |
| hedgeberg | oh hey you already spoke to john about the fact im planning to contrib on xray? | 06:52 |
| hedgeberg | and, yeah, will let you know, just atm im task juggling | 06:52 |
| hedgeberg | im in the rare "remove things from the todo list" mood, instead of the opposite | 06:53 |
| hedgeberg | so im checking things off | 06:53 |
| digshadow | (this is john) | 06:53 |
| digshadow | Gotcha, so for now you are mostly lurkijng? | 06:53 |
| hedgeberg | oooooh that makes sense | 07:14 |
| hedgeberg | I figured your username would be like, jdm or something? or for some reason I figured you weren't on irc? no idea why I made that assumption | 07:15 |
| hedgeberg | and, yeah, rn just lurking while I try to get as much checked off of my todolist before I go back to work next monday. | 07:16 |
| hedgeberg | feel like I have more free time while working than less >.< | 07:16 |
| hedgeberg | that being said, if I work on this anywhere, it will quite possibly be while I'm at work, since my place of work (or at least my group there) encourages using free time for self research projects | 07:17 |
| hedgeberg | its infosec, so like, any breadth-learning is appreciated if you can just insinuate that it may come in useful down the road | 07:19 |
| hedgeberg | and if theres one thing ive learned over the last few years its that freaking everything is a vulnerability surface | 07:20 |
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| noopwafel | digshadow: productive for my understanding, not so much for prjxray so far :) | 07:59 |
| digshadow | hedgeberg: cool let me know then | 08:01 |
| digshadow | noopwafel: gotcha | 08:01 |
| noopwafel | digshadow: is the way you hooked xadc into tilegrid a good example for how to hack something in? | 08:08 |
| noopwafel | I realize I could just ask you to do it.. :-) but trying to piece together how this works is good for me | 08:08 |
| digshadow | noopwafel: its not a bad place to start, but I don't think it LOCs because there is only one in the ROI | 08:11 |
| noopwafel | inspecting bitread output is already helpful to work out baseaddr and confirm things are kinda as expected for the GTP | 08:11 |
| digshadow | maybe a good project to start with would be to convert BRAM to the new style | 08:11 |
| digshadow | we know that its going to break outside of the ROI (there is a ticket) | 08:11 |
| digshadow | I also know that is pretty straightforward, like XADC | 08:12 |
| digshadow | (new tilegrid style) | 08:12 |
| digshadow | this would also provide you with a known good tilegrid.json that you could check before / after | 08:12 |
| digshadow | https://github.com/SymbiFlow/prjxray/issues/342 | 08:13 |
| tpb | Title: tilegrid: BRAM breaks on full part · Issue #342 · SymbiFlow/prjxray · GitHub (at github.com) | 08:13 |
| noopwafel | stupid question time, 'full part'? | 08:16 |
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| mithro | kgugala: https://github.com/SymbiFlow/symbiflow-arch-defs/issues/310 | 08:17 |
| tpb | Title: Rename Artix 7 directory to something "Xilinx Series 7" · Issue #310 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 08:17 |
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| noopwafel | (I mean I saw the comment about the PCIE block cutting out some BRAM, just want to make sure that this is not meant to target 200T or something) | 08:21 |
| mithro | digshadow: I gave you edit access to https://docs.google.com/drawings/d/1eqP44TDeaLLEO0CaEjn_bxorOV3iAXmelFsyzMi4yVI/edit | 08:24 |
| tpb | Title: Project X-Ray - File Diagram - Google Drawings (at docs.google.com) | 08:24 |
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| mithro | digshadow: Would be good to check the diagram on the left side | 08:43 |
| mithro | mgielda[m]: Take a look at https://docs.google.com/drawings/d/1eqP44TDeaLLEO0CaEjn_bxorOV3iAXmelFsyzMi4yVI/edit too | 08:43 |
| tpb | Title: Project X-Ray - File Diagram - Google Drawings (at docs.google.com) | 08:44 |
| digshadow | noopwafel: we run in a "region of interest" currently, a subset of a full FPGA | 08:48 |
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| digshadow | if you are able to run a fuzzer, open up a .dcp in vivado. You'll see a purple box upper left | 08:49 |
| digshadow | (assuming you are doing artix7) | 08:49 |
| digshadow | mithro: I think ffconfig is part of the CLB | 08:50 |
| digshadow | we should rename all clb fuzzers to have clb in the name | 08:50 |
| digshadow | oh nvm I misread your diagram | 08:50 |
| noopwafel | yeah, I saw the env variables for ROI :) | 08:51 |
| digshadow | I'm still a little confused about your left/right column though. should bram-data and bram-config be together there? | 08:52 |
| digshadow | noopwafel: if those were expanded for the full chip, bram tilegrid breaks | 08:52 |
| noopwafel | (btw what do the numbers in the fuzzer directory names mean? they're just categorization and otherwise arbitrary other than the run order?) | 08:52 |
| digshadow | noopwafel: they are for orgnization only. They are meaningless, other than generally fuzzers that must be run first have lower numbers | 08:53 |
| noopwafel | thanks :) | 08:56 |
| mithro | digshadow: I think the we should do a bit of fuzzer renaming.... | 09:16 |
| mithro | digshadow: Maybe XXX-tiletype-XXXX ? | 09:23 |
| mithro | digshadow: The right column is "pips" the left column is "config" | 09:24 |
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| mithro | acomodi: -> alias cdb='cd $(pwd | sed -e"s,$(git rev-parse --show-toplevel),$(git rev-parse --show-toplevel)/build," -e"s,build/build,,")' | 10:13 |
| digshadow | mithro: sure, that naming scheme works for me | 11:08 |
| digshadow | mithro: https://twitter.com/bml_khubbard/status/1066403225291517952 | 11:12 |
| digshadow | do you have any idea the pricing they are targeting on that ("maker friendly pricing") | 11:12 |
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| digshadow | mithro: filed https://github.com/SymbiFlow/prjxray/issues/438 | 11:20 |
| tpb | Title: Clean up fuzzer names · Issue #438 · SymbiFlow/prjxray · GitHub (at github.com) | 11:20 |
| mithro | kgugala: The rebuild of Yosys will be here -> https://travis-ci.com/SymbiFlow/conda-packages/builds/96169968 | 11:49 |
| tpb | Title: Travis CI - Test and Deploy with Confidence (at travis-ci.com) | 11:49 |
| mithro | digshadow: No idea on pricing | 12:07 |
| digshadow | mithro: there was also at least one jab there asking for FOSS tools | 12:08 |
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| torgax | How do I get started devving for FPGA's with OSS software? Want to write a CPU. | 18:31 |
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| bitmorse_ | if you're a beginner, you could start by looking at the concepts (e.g. here https://www.nandland.com/). if you're more advanced, check out https://github.com/enjoy-digital/litex and the environment https://github.com/timvideos/litex-buildenv - i use tinyfpga bx board and a radiona ULX3S ECP5 fpga, as they are supported at the moment. | 20:29 |
| tpb | Title: Nandland: FPGA, VHDL, Verilog Examples & Tutorials (at www.nandland.com) | 20:29 |
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