| *** tpb has joined #litex | 00:00 | |
| *** rj has quit IRC | 00:03 | |
| *** jon__ has joined #litex | 00:04 | |
| *** pftbest has joined #litex | 00:05 | |
| *** jon_ has quit IRC | 00:07 | |
| *** rj has joined #litex | 00:08 | |
| *** Degi_ has joined #litex | 00:10 | |
| *** pftbest has quit IRC | 00:10 | |
| *** Degi has quit IRC | 00:13 | |
| *** Degi_ is now known as Degi | 00:13 | |
| *** rj has quit IRC | 00:33 | |
| *** rj has joined #litex | 00:40 | |
| *** kgugala has joined #litex | 00:41 | |
| *** jon__ has quit IRC | 00:42 | |
| *** jon_ has joined #litex | 00:43 | |
| *** rj has quit IRC | 01:05 | |
| *** jon_ has quit IRC | 01:56 | |
| *** jon_ has joined #litex | 01:57 | |
| *** boardrunner has joined #litex | 02:11 | |
| boardrunner | trying to get the usb3_pipe example running either on NeTV or Versa, but when I run ./versa_ecp5.py the .v file that is generated can't be synthesized because sys_rst is driven by multiple outputs: ERROR: Net 'bridge_count_TRELLIS_FF_Q_CE[0]' is multiply driven by cell ports FD1S3BX_1.Q and FD1S3BX_5.Q | 02:18 |
|---|---|---|
| boardrunner | any ideas what might be happening? | 02:18 |
| boardrunner | here are a few more lines when trying to run build_lattice_versa_ecp5.sh to synthesize the design: https://pastebin.com/XLPHzm0a | 02:21 |
| tpb | Title: 20.51. Executing CHECK pass (checking for obvious problems).Checking module la - Pastebin.com (at pastebin.com) | 02:21 |
| *** proteusguy has quit IRC | 03:15 | |
| *** boardrunner has quit IRC | 03:52 | |
| *** Bertl is now known as Bertl_zZ | 04:00 | |
| *** boardrunner has joined #litex | 04:15 | |
| *** boardrunner has quit IRC | 04:18 | |
| *** chipdsgr has joined #litex | 04:18 | |
| *** jon_ has quit IRC | 04:33 | |
| *** jon_ has joined #litex | 04:49 | |
| *** jon_ has quit IRC | 05:37 | |
| *** pftbest has joined #litex | 05:46 | |
| *** pftbest has quit IRC | 05:46 | |
| *** pftbest has joined #litex | 06:07 | |
| *** pftbest has quit IRC | 06:11 | |
| *** pftbest has joined #litex | 06:17 | |
| _florent_ | boardrunner: I just fixed the usb3_pipe build with https://github.com/enjoy-digital/usb3_pipe/commit/d6e27d7d35503b3356b937e477e2a13ff98f546e (was related to the reset now directly integrated in the ECP5PLL wrapper) and also did small simplifications that are now possible with LiteX. | 07:54 |
| _florent_ | but this project was an experiment and I would still recommend having a USB3 analyzer when testing it. The ECP5 port was not very stable but the Artix7/Kintex7 port was able to enumerate correctly and have the link stay up (but not with all computers). | 07:57 |
| _florent_ | You can also look at Luna project that used this work as a basis for the USB3 support, there are probably been various improvements but I'm not well aware of them | 08:03 |
| _florent_ | there are/there has | 08:03 |
| chipdsgr | did you use the ECP5-5G dev kit? (wondering if the lack of 5Gbps SERDES could have been the reason for the lack of stability) | 08:21 |
| *** RaivisR has joined #litex | 08:26 | |
| chipdsgr | btw awesome fast fix :D I'm able to synthesize things now, thanks! | 08:27 |
| RaivisR | good time of day, I noticed interesting thing, every time I re-build simple design for ecp5, sys_clk max frequency reported is different. no changes to the design itself. is it a known thing? | 08:29 |
| *** rom16 has joined #litex | 08:43 | |
| rom16 | hi, I'm currently using Litex to generate SoC for testing on FPGA. I'm looking for a path to move the design from FPGA to ASIC (remove vendor IP, create blackbox, etc). Have anyone ever attempt this before? | 08:45 |
| chipdsgr | rom16: checkout OpenROAD/OpenLane and the skywater project for people experimenting going from RTL to ASIC | 08:47 |
| rom16 | we have access to commercial tools so no need for the skywater project. We already have experience going from RTL to ASIC. The problem is the RTL generation from Litex | 08:48 |
| rom16 | (thanks for the tips though) | 08:48 |
| rom16 | I'm using Litex because Chipyard is a mess. Had one chip taped-out from it and it's just horrible to continue our work with it. | 08:49 |
| chipdsgr | oh wow, very cool! out of curiosity what tools did you use to do the layout of that design? | 08:54 |
| Melkhior | @rom16 Would be nice to have an ASIC version of Litex, no idea about seasibility. Assuming you're looking for a RISC-V SoC generator, maybe you can investigate https://www.esp.cs.columbia.edu/ as I think they're targeting ASIC as well | 08:59 |
| tpb | Title: ESP - open SoC platformESP | ESP - open SoC platform (at www.esp.cs.columbia.edu) | 08:59 |
| Melkhior | s/seasibility/feasibility/ | 09:01 |
| rom16 | chipdsgr I use the standard industry tools: DC for synthesis, ICC2 for PnR, PT for STA and Calibre for DFM | 09:02 |
| rom16 | Melkhior I'm aiming to do it using Litex, probably going to take a month or 2 (it's just a master thesis, not my main job so it's going to take a bit of time) | 09:03 |
| rom16 | planned to do the LiteDRAM for Altera parts (Cyclone IV) after the chip too | 09:04 |
| Melkhior | @rom16 a chip during a master thesis ? lucky you :-) | 09:04 |
| rom16 | not during, before... | 09:04 |
| rom16 | an IoT-oriented MCU with RISC-V core is my final thesis for M.S. (2.5 years from now) | 09:05 |
| Melkhior | @rom16 hehe kids today have all the luck:-) #oldfart ;-) | 09:05 |
| rom16 | @Melkhior I'm not doing all the things alone:D I have a friend working on the analog portion of the chip for me | 09:07 |
| Melkhior | @rom16 ESP also has accelerators for AI in mind, which might be of interest fo you | 09:07 |
| chipdsgr | how's it going to talk to the outside world? | 09:07 |
| chipdsgr | any RF? | 09:07 |
| rom16 | we don't have any people with experience in RF IC design, so sadly no | 09:08 |
| rom16 | I guess we can use a SPI-based external IC | 09:08 |
| rom16 | and if we need DRAM, we also don't have any IP for it... so FPGA will have to serve as a medium for it | 09:09 |
| Melkhior | @rom16 So you would have an ASIC with not much external connection except some 'custom' stuff to an FPGA, then the FPGA talks to the outside world? | 09:15 |
| rom16 | @Melkhior: I would have an ASIC with some external connection, except for some special connection which need an FPGA to function (DRAM is a PITA to do IP for) | 09:19 |
| rom16 | (and some people called RF "black magic") | 09:19 |
| Melkhior | @rom16 OK, nice, hopefully Litex will fit the bill :-) | 09:19 |
| rom16 | well, considered that writing python is familiiar and less error-prone than scala (looking at you Chisel!), I think the feasibility is high | 09:20 |
| rom16 | I'll come back to this IRC or push something to github when I make some progress | 09:22 |
| rom16 | stay tuned! | 09:22 |
| _florent_ | rom16: interesting, to create ASIC with LiteX, the path would probably be to create build backend, similar to what we have for the different FPGA vendor, expect that you'll be targeting your ASIC toolchain with its own primitives | 09:41 |
| _florent_ | This would already allow building the designs with simple primitives, then you could create specialized wrapped for the PLL, specialized PHYs for LiteDRAM, LiteETH, etc... | 09:42 |
| _florent_ | But for simple LiteDRAM PHYs (ex SDRAM), simple LiteETH PHYs (ex MII, RMII), just adding the build backend should be enough since LiteX will be lowering the primitives automatically | 09:44 |
| _florent_ | rom16: feel free to ask it you need directions to get started and setup your ASIC flow with LiteX, that was not the primary aim of the project but we see more and more interest for this | 09:50 |
| rom16 | _florent_: thanks for the direction. I'm more of a RTL design engineer, so my approach would be almost similar. I'd like to replace the vendor IP with blackbox (only contain input and nothing else) so I'd be integrating the ASIC IP later on if I can. | 10:08 |
| *** Bertl_zZ is now known as Bertl | 10:08 | |
| rom16 | and for the top chip IO, it would be similar to the board definition (I think, I haven't take a long look at it yet) | 10:12 |
| rom16 | I don't really need the backend, since we already have a very solid backend at work. All I need for now is the synthesizable RTL. | 10:13 |
| *** RaivisR has quit IRC | 10:21 | |
| *** RaivisR has joined #litex | 10:21 | |
| *** rom16 has quit IRC | 10:36 | |
| *** TMM has quit IRC | 10:44 | |
| *** TMM has joined #litex | 10:44 | |
| *** RaivisR_ has joined #litex | 11:38 | |
| *** RaivisR has quit IRC | 11:42 | |
| *** proteusguy has joined #litex | 12:14 | |
| *** Melkhior has quit IRC | 12:47 | |
| *** Melkhior has joined #litex | 12:57 | |
| somlo | for anyone interested in getting Fedora to run on Litex, here's a link with all the gory details (and a qemu vm I used as "source") of what happened so far... https://github.com/litex-hub/linux-on-litex-rocket/issues/10#issuecomment-825276485 | 13:41 |
| shoragan | somlo, when trying to synthetize a rocket core with the code in https://github.com/litex-hub/pythondata-cpu-rocket, it complained that it couldn't find some port. are you using a different source? | 13:49 |
| shoragan | 8.4.3. Analyzing design hierarchy.. | 13:49 |
| shoragan | ERROR: Module `ExampleRocketSystem' referenced in module `lambdaconcept_ecpix5' in cell `ExampleRocketSystem' does not have a port named 'resetctrl_hartIsInReset_0'. | 13:49 |
| *** rj has joined #litex | 14:29 | |
| *** rj has joined #litex | 14:30 | |
| *** kgugala_ has joined #litex | 17:31 | |
| *** kgugala has quit IRC | 17:32 | |
| *** kgugala has joined #litex | 17:48 | |
| *** kgugala_ has quit IRC | 17:50 | |
| *** TMM has quit IRC | 18:08 | |
| *** TMM has joined #litex | 18:08 | |
| somlo | shoragan: assuming you have the latest of everything in litex, it might be about the yosys version -- mine is at git commit 26e01a6 (as of March 10 2021 or thereabouts) | 18:11 |
| nickoe | Is there a way to re-use the litex_server --jtag ... instance with the --load option? | 18:15 |
| nickoe | for the target scripts | 18:15 |
| shoragan | somlo, maybe it's related to https://github.com/enjoy-digital/litex/commit/116c2f15494af7cd51af74569f122ee245fd6eb4#diff-e8b2dd6d0203ed0aaf32e33305d3697381d4da6ec3f56dabe8470306e01cb0e9L124 | 18:15 |
| shoragan | it's now defined as = Open() | 18:15 |
| shoragan | somlo, i've got yosys d061b0e41a2 and litex fb8f45be7330fd | 18:19 |
| shoragan | i'll try with your version | 18:21 |
| nickoe | What does this vivado critical warning really mean? I have an Artix7. | 18:26 |
| nickoe | CRITICAL WARNING: [Timing 38-472] The REFCLK pin of IDELAYCTRL IDELAYCTRL is not reached by any clock but IDELAYE2 IDELAYE2_10 has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property value. | 18:26 |
| shoragan | somlo, even with yosys 26e01a67db, i get the same error. is your litex newer than 116c2f15494? | 18:26 |
| *** acathla has quit IRC | 19:26 | |
| somlo | shoragan: I keep my litex sync-ed up with enjoy-digital (and litex-hub) upstream, so it's the newest available | 19:52 |
| shoragan | somlo, hmm. did you regenerate your rocket core? | 19:53 |
| nickoe | Hmm, how does one buffer up a couple of words of serial data in a migen fsm? | 19:58 |
| nickoe | To be consumed at a lower rate. | 19:58 |
| somlo | shoragan: it's the rocket core currently in pythondata-cpu-rocket -- I should probably update it from chipsalliance/rocket-chip and see if any new breakage was introduced, but litex should work with the pythondata-cpu-rocket as is | 20:10 |
| somlo | shoragan: what board are you building for? | 20:10 |
| shoragan | somlo, ecpix-5 85k | 20:10 |
| shoragan | your prebuild bitstream works fine | 20:11 |
| shoragan | hmm, then i must be missing something else. i don't see how i'd get that 'resetctrl_hartIsInReset_0' error when using the same pythondata-cpu-rocket and litex | 20:12 |
| somlo | hmmm... I just started a build for ecpix5 and am currently at "8.24.*" in yosys | 20:13 |
| somlo | grasping at straws here, but maybe explicitly remove your build directory before restarting a build? Sometimes I get weird errors if I don't do that... | 20:14 |
| shoragan | somlo, i see "Warning: Max frequency for clock '$glbnet$sdrio_clk': 17.24 MHz (FAIL at 50.00 MHz)" in the log, but i heard that that is unlikely to be critical | 20:15 |
| shoragan | somlo, ok. | 20:16 |
| *** acathla has joined #litex | 20:42 | |
| *** pftbest has quit IRC | 20:50 | |
| *** pftbest has joined #litex | 20:50 | |
| somlo | is there an example of how to set up linux (probably on vexriscv) to directly utilize the liteuart? Right now, I'm using "console=hvc0" in bootargs (and grepping through linux-on-lite-vexriscv I find the same thing there), and that essentially traps into machine mode and has the m-mode emulator deal with the UART (BBL in my case) | 21:18 |
| shoragan | somlo, there is drivers/tty/serial/liteuart.c, which binds to the "litex,liteuart" dt compatible. from looking at the source it should register ttyLXU0 | 21:28 |
| shoragan | (at least that's the way it would work on arm socs ;) | 21:29 |
| somlo | shoragan: tried "console=ttyLXU0" in bootargs (have the liteuart compiled in the kernel, and the DTS obviously correct (since BBL uses it too before passing it to linux) | 21:31 |
| somlo | but I get nothing after BBL :( | 21:32 |
| shoragan | if you can boot a different way, it should show up in /proc/tty/drivers | 21:38 |
| shoragan | you could test it with echo/cat/stty from there | 21:38 |
| somlo | I see "liteuart /dev/ttyLXU 253 0 serial" | 21:39 |
| shoragan | then you should also have a /dev/ttyLXU0 | 21:42 |
| somlo | if I then "mknod /dev/ttyLXU c 253 0" I can echo things into it and see them show up on the console :) | 21:42 |
| shoragan | with mount -t devtmpfs none /dev it should already be there | 21:42 |
| shoragan | so the driver works :) | 21:43 |
| shoragan | you have CONFIG_SERIAL_LITEUART_CONSOLE=y? | 21:43 |
| somlo | yes | 21:44 |
| somlo | hm, I should mount devtmpfs in initrd, rather than have a few nodes manually created... Thanks for pointing that out :) | 21:46 |
| somlo | (still not sure why the booting kernel won't use the device if passed in on the kernel command line, but that's orthogonal :) | 21:46 |
| shoragan | check /proc/cmdline and /proc/console | 21:47 |
| shoragan | to be sure that you don't have any other console (primary) console | 21:48 |
| somlo | right now I have "console=hvc0" on the bootargs, and "hvc0 -W- (EC p ) 229:0" in /proc/consoles; but that's how I got it to output anything at all -- if I set "console=ttyLXU0" in bootargs instead, I get nothing at all | 21:50 |
| shoragan | you could try using earlycon via sbi, maybe you can see any error messages that way. i don't have any other ideas right now :/ | 21:50 |
| somlo | fair enough, thanks for the brainstorm :) | 21:50 |
| shoragan | maybe ttyLXU0 needs a ,115200n8? | 21:51 |
| shoragan | https://patchwork.kernel.org/project/linux-riscv/patch/[email protected]/ | 21:52 |
| tpb | Title: [1/3] tty/serial: Add RISC-V SBI earlycon support - Patchwork (at patchwork.kernel.org) | 21:52 |
| Melkhior | @somlo the default command line for linux-on-litex-vexriscv is in the DTS https://github.com/enjoy-digital/litex/blob/bfb90f56251abb0b7164ec3506069591759c2998/litex/tools/litex_json2dts.py#L49 | 21:53 |
| Melkhior | (e.g. it's where I replace console=liteuart by fbcon=map:0 to get the graphical console on the framebuffer) | 21:53 |
| Melkhior | late here, good night and good luck :-) | 21:54 |
| somlo | so it's "console=liteuart" then, not "console=ttyLXU0" ? | 21:56 |
| somlo | let me try that... | 21:56 |
| somlo | Melkhior -- thanks, that actually worked! | 21:59 |
| *** pftbest has quit IRC | 22:58 | |
| *** pftbest has joined #litex | 23:04 | |
| *** lf has quit IRC | 23:12 | |
| *** lf has joined #litex | 23:13 | |
| *** pftbest has quit IRC | 23:16 | |
| *** pftbest has joined #litex | 23:36 | |
| *** pftbest has quit IRC | 23:41 | |
Generated by irclog2html.py 2.17.2 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!