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| _florent_ | Hi | 06:41 |
|---|---|---|
| _florent_ | nickoe: I fix the issue you saw in simulation recently | 06:41 |
| _florent_ | fixed | 06:41 |
| _florent_ | litex_sim | 06:42 |
| _florent_ | litex_bare_metal_demo --build-path=build/sim | 06:42 |
| _florent_ | litex_sim --ram-init=demo.bin | 06:42 |
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| _florent_ | with this, the donut command is now more generous :) and can provide you donuts until you press a key | 06:44 |
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| _florent_ | chmouss: Sorry, I've not been able to do the test yesterday, but just did it now: | 06:45 |
| _florent_ | python3 -m litex_boards.targets.lattice_versa_ecp5 --cpu-type=None --with-etherbone --csr-csv=csr.csv --build --load | 06:45 |
| _florent_ | litex_server --udp | 06:45 |
| _florent_ | litex_cli --regs | 06:46 |
| _florent_ | works on my setup | 06:46 |
| _florent_ | I can share the bitstream if you want to test it | 06:47 |
| _florent_ | https://github.com/litex-hub/litex-boards/files/6341217/lattice_versa_ecp5_etherbone_test_2021_04_20.zip | 06:49 |
| _florent_ | chmouss: I also tested with the CPU (ie without --cpu-type=None) and it's also working | 06:54 |
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| chmouss | _florent_: Thanks, I see exactly the same behaviour with your bitstream so it must be an issue on my side (WSL maybe?). Will try with another computer. | 07:46 |
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| Melkhior | _florent_ You were right - seems HW was OK, but i wasn't enabling the interrupts in the driver :facepalm: | 07:59 |
| Melkhior | I have event in /dev/input/event0 now when I hit a key | 08:00 |
| Melkhior | at least when arkbd serio enables the keyboard which isn't reliable (yet) | 08:01 |
| _florent_ | Melkhior: ok nice | 08:19 |
| _florent_ | sajattack[m]: Sorry, I'll look at the Acorn CLE215 / SPIFlash today | 09:33 |
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| mithro | Potential VexRISC-V challenger! http://www.informatik.uni-bremen.de/agra/doc/work/date21_unibooth_microrv32.pdf -- MicroRV32 - A SpinalHDL based RV32I - Implementation Suitable for FPGAs -- No idea how it actually compares.... | 14:33 |
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| nickoe | _florent_: Ah cool!!! I like generous donuts. | 14:52 |
| nickoe | _florent_: I wonder what change it took, I can't seem to find a related commit in the litex repo | 14:58 |
| _florent_ | nickoe: I can probably find it | 14:58 |
| _florent_ | https://github.com/enjoy-digital/litex/commit/a1e54671beac463baa5809bb1192dab18cbcc4c8#diff-ea9d572dc54c0f6bab20cb2448efd4ed4049d9c7d4b5706ecf933d7acaa8ee9b | 14:59 |
| nickoe | _florent_: Hmm, ok, cool, so it was something about the CR vs LF things as you mentioned | 15:00 |
| _florent_ | yes, a workaround that has been introduced at some point or for a specific use case and that was not longer required | 15:01 |
| nickoe | I am trying to catch up with my SDRAM to AXI strema | 15:01 |
| nickoe | I got the tracing working with the analyzer, but I think I should be able to trace for way longer just using the --trace option to litex_sim, right? | 15:02 |
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| _florent_ | yes indeed | 15:05 |
| _florent_ | it's also possible to enable/disable the tracing from your logic dynamically | 15:05 |
| _florent_ | to only capture the parts that are relevant and avoid too large traces | 15:05 |
| nickoe | I don't seem to get a vcd, I am doing "litex_sim --ram-init demo.bin --trace --trace-start 1 --trace-end 2000" | 15:06 |
| nickoe | So that is withourt the analyzer | 15:06 |
| nickoe | What am I missing? | 15:06 |
| nickoe | mmm, there is a file in the build dir! but it is empt? | 15:09 |
| nickoe | https://dpaste.com/2XTKRCNAH.txt | 15:09 |
| nickoe | Can I make the simulation auto stop when hitting trace end? | 15:11 |
| mithro | https://twitter.com/SAFARI_ETH_CMU/status/1384371656718696449?s=20 - something that LiteDRAM could do? | 15:19 |
| nickoe | mithro: Are you replyig to me or asking anyone in the channel? | 15:23 |
| mithro | Anyone. | 15:25 |
| _florent_ | nickoe: it seems we may have broke trace-start/end with recent changes in the simulation, I would have to look at that. You can eventually just use --trace and a Finish in your Simulation. | 15:28 |
| _florent_ | something like this: | 15:29 |
| _florent_ | https://www.irccloud.com/pastebin/qwkjWQ66/ | 15:29 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 15:29 |
| nickoe | _florent_: for the record I have not pull since late february, so maybe I should just do it and hope there are no new hurdles? | 15:29 |
| nickoe | "a finish"? | 15:29 |
| nickoe | I just ctrl+c it | 15:29 |
| nickoe | is that wrong? | 15:30 |
| nickoe | ah, there is a "finish" | 15:30 |
| nickoe | (your paste) | 15:30 |
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| _florent_ | If you add the code snippet to litex_sim.py and run litex_sim --trace | 15:31 |
| nickoe | yeah, just added it to my own sim script | 15:31 |
| _florent_ | it will finish the simulation after 2000 cycles and the waveform will be in build/sim/gateware/sim.vcd | 15:32 |
| nickoe | That do appear to work! | 15:32 |
| nickoe | So if that bug is recent, it was also there in late january fwiw | 15:33 |
| _florent_ | You can also display the values of signals during the simulation, for example something I have in an auto-checking simulation at the end: | 15:33 |
| nickoe | So I guess I can somehow combine that wiht the analzer's triggeR? | 15:33 |
| nickoe | That sounds awesome | 15:33 |
| _florent_ | https://www.irccloud.com/pastebin/vA4OdwrD/ | 15:33 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 15:33 |
| _florent_ | If you don't really need to go to hardware and can do it in simulation, I recommend continue in simulation | 15:34 |
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| _florent_ | The analyzer is useful for debugging things that are difficult to simulate, or to understand the behaviour on the hardware before eventually try to reproduce it in simulation and fix the issue | 15:35 |
| nickoe | Yeah, I mean, for the part I want to wrap my head around on how to get work... I want to run it in simulation to debug and verify it easier. But IIRC, I may also have had some trouble loading a boot.json or --ram-init together with the --rom-init? | 15:36 |
| _florent_ | mithro: Thanks nice. It seems a bit similat to ComputeDRAM no? http://parallel.princeton.edu/papers/micro19-gao.pdf | 15:36 |
| nickoe | Is there any recommendation on how to maintain a project that is using litex stuff? | 15:37 |
| nickoe | I mean, how to structure the repos | 15:37 |
| _florent_ | IIRC ComputeDRAM has been tested with LiteDRAM | 15:37 |
| nickoe | _florent_: But with the --trace option I don't get the singals I had with the analyzer? Like these https://github.com/nickoe/litex-boards/blob/255d811bc1342d2a3d5a058787fcf91700c8e3e9/litex_boards/targets/mars_ax3_sim_litex.py#L304-L307 | 15:39 |
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| _florent_ | with the --trace args you get all the signals of the design, so the user_led should be there | 15:39 |
| nickoe | It looks like the modules I get are VexRiscv, sd_link, sd_phy | 15:39 |
| _florent_ | you should see your signals at the top level | 15:40 |
| nickoe | are they are in the TOP | 15:40 |
| nickoe | I mean "ahhh" | 15:40 |
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| nickoe | Thank you for the tips! | 15:41 |
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| _florent_ | nickoe: for example project managed externally, you can look at: | 15:43 |
| _florent_ | https://github.com/enjoy-digital/pcie_analyzer | 15:43 |
| _florent_ | https://github.com/enjoy-digital/colorlite | 15:43 |
| _florent_ | https://github.com/enjoy-digital/pcie_screamer | 15:43 |
| _florent_ | https://github.com/enjoy-digital/litesata_axiom | 15:44 |
| _florent_ | There are just some examples, you can also find useful resources in the Wiki: | 15:45 |
| _florent_ | https://github.com/enjoy-digital/litex/wiki/Tutorials-Resources | 15:45 |
| _florent_ | https://github.com/enjoy-digital/litex/wiki/Projects | 15:45 |
| nickoe | yay, I can see the "rolling" leds for the LED chanser 2s sim :D | 15:45 |
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| Finde | _florent_ is correct about ComputeDRAM | 15:55 |
| mithro | Is the ComputeDRAM in a public repo anywhere? | 16:06 |
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| nickoe | _florent_: Can I filter the vcd at trace time, such that I don't get some modules dumped? | 17:46 |
| nickoe | I mean together with the --trace? | 17:46 |
| _florent_ | it's possible to configure the trace depth with Verilator, but not sure this is exposed in LiteX | 17:48 |
| _florent_ | Not sure for tracing only selected modules with Verilator, but at least I know this is not supported in LiteX... | 17:50 |
| nickoe | OK, thanks. | 17:59 |
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| nickoe | _florent_: If I make my own "litex" project specific repo, am I required to add the "Copyright 2012-2020 / LiteX-Hub community" as I am essentially just making it "alike" but not really forking it as it is a new board? | 19:04 |
| nickoe | My project being MIT licensed | 19:05 |
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| sajattack[m] | <_florent_ "sajattack: Sorry, I'll look at t"> yay | 19:22 |
| Finde | mithro: no not yet, the original version was based on softmc which is kind of a strange project | 19:27 |
| Finde | don't know all the details of the current dev status with litedram | 19:27 |
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| _florent_ | nickoe: for the copyright, this is your project :) so you are free to use your copyright. Happy to have feedback about your project or what you do with the tools. | 20:08 |
| nickoe | Ok, cool | 20:10 |
| nickoe | _florent_: This is the current state of my simulation :S https://github.com/nickoe/litex-boards/blob/mars_ax3_sim/litex_boards/targets/mars_ax3_sim_litex.py | 20:13 |
| nickoe | But I am slightly lost with _MyDMA() | 20:13 |
| nickoe | which is based directly from the litex_sim becuase I had trouble tracing stuff initially | 20:18 |
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| nickoe | Hmm, how long does it take for the simulator to laod a 4k file form tftp boot from a boot.json? | 21:30 |
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| nickoe | mm, ok, if I remove my first thing it boots the demo.bin just fine... it was test_data.cs16": { "0x41000000", demo.bin": "0x40000000" }, but just {"demo.bin": "0x40000000"} seem to work quick! | 21:44 |
| nickoe | mmm, it just .mmm, does not seem to like that second file | 21:49 |
| nickoe | or location | 21:50 |
| nickoe | Are there certain requirements for the file? maybe size boundaries? | 21:52 |
| nickoe | hmm, no, my file is exactly 4kiB | 21:54 |
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