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| thorns514 | is there a trick to getting litescope to trigger properly on a soc with multiple clock domains? | 01:25 |
|---|---|---|
| thorns514 | every time I add a valenty usb core for debug bridge (instead of uart) with its 12mhz/48mhz clocks, the litescope_cli never waits for my cyc trigger, it just dumps immediately... | 01:26 |
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| Yam | Hello, I saw some support for LPDDR4 on Kintex 7. What is the status on it? Is it working yet ? | 03:28 |
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| lkcl | _florent_, morning, you received my messages with the patches? would it be better to raise a bugreport on bugs.libre-soc.org (oh, and attach some $EUR to it? :) ) | 09:29 |
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| _florent_ | thorns514: You can specify the sampling clock domain with the clock_domain parameter: https://github.com/enjoy-digital/litescope/blob/master/litescope/core.py#L229 | 10:10 |
| _florent_ | Yam: The LPDDR4 support on Kintex7 is working yes, Antmicro has been working on it and validated it at up to 1000MT/s for now. The work is already integrated in LiteX/LiteDRAM. Antmicro is now working on improving the max clock freq now. If you have specific questions, feel free to ask here, I or kgugala__ could give you more infos. | 10:13 |
| Yam | Thank you, as I understand, I need two banks, one with 1.8V, and another with 1.1V, right ? I saw the schematic for the test board, but is there a schematic for the test "RAM" modules? | 10:18 |
| Yam | Oh, I actually just saw the schematic for the module | 10:20 |
| Yam | wait, not the module. but the pins map directly to LPDDR4 pins, right? I might try to build a board using the LPDDR4. Will let you know how it goes. | 10:28 |
| _florent_ | Yam: The hardware is using DIMMs to easily swap the LPDDR4 module, but it's similar to a module directly connected to the FPGA yes | 11:01 |
| Yam | _florent_ I saw the test board here,https://github.com/antmicro/lpddr4-test-board , is the DIMM open source ? | 11:03 |
| zyp | https://github.com/antmicro/lpddr4-testbed | 11:06 |
| Yam | zyp Thank you | 11:11 |
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| _florent_ | lkcl: I received the messages yes, but was not sure what to answer yet: I kind of understood in the other IRC channels during the last months that LiteX was the source of so much miseries for you, that you would not recommend using it for any serious work and that you were going to develop an alternative, has it changed? :) Most developers here (me included) just want to have fun and enjoy what they do, working | 11:15 |
| _florent_ | together without any ambition to do better than X or compare to Y, you got direct help from me, reused lots of our existing work to validate/debug your CPU (including the recent work at that time on Microwatt) and as a result we get what I described just above? I don't necessarily want you to like LiteX, but you seem to be playing a strange game, no? | 11:15 |
| zyp | are there any examples anywhere of using the HyperRAMX2 core from litehyperbus? | 11:41 |
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| pftbest | The wishbone interface on litedram does not support bursts, right? So if i want a higher throughput i need to use axi interface? | 11:55 |
| _florent_ | zyp: This has been designed by Greg Davill, he seems to use it here: https://github.com/gregdavill/DiVA-firmware/blob/main/gateware/rtl/streamable_hyperram.py | 11:56 |
| zyp | yeah, I went digging and is looking through that now | 11:57 |
| _florent_ | pftbest: Indeed, for now for burst you can use the Native interface or AXI interface. Adding burst support to the Wishbone interface should not be too much work but don't think it's supported currently | 11:58 |
| pftbest | Is there a way to switch to another interface in litex? as i understand litex is using wishbone by default. And I'd like it to keep doing read leveling, and other configuration | 12:06 |
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| _florent_ | pftbest: In fact the leveling is done through the CSRs and the default connection for the MMAP between the SoC and DRAM is a wishbone interface | 12:11 |
| pftbest | so i just need to disconnect it from the soc memory map and the CSRs will still keep working? | 12:12 |
| _florent_ | yes, or you add another DRAM port with crossbar.get_port and use it directly in your logic | 12:17 |
| pftbest | oh, i can have more than 1 port at the same time? that sounds very good, thanks! | 12:20 |
| _florent_ | yes, you can request addionnal port, the controller will arbitrate the accesses. | 12:22 |
| _florent_ | For example here, for the optional BIST (Hardware Build-In Self Test) we request two additional ports: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc.py#L1254-L1256 | 12:23 |
| pftbest | i'll try, thank you | 12:25 |
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| Melkhior | _florent_ Worked on getting a keyboard over the week-end, but I'm stuck on the interrupt. LInux sends the command and the keyboard answers (says my logic analyzer), and if I probe the CSR I see the keyboard's answers in Linux. If I force probing after sending a command, I can event get the whole thing to register as a keyboard and have a | 13:16 |
| Melkhior | /dev/input/event0 entry. | 13:16 |
| Melkhior | But I can't figure out how to get the interrupt to trigger in Linux, it never triggers and I always have 0 in /proc/interrupts | 13:16 |
| Melkhior | My IRQ code is here: https://pastebin.com/1HrGj5wK | 13:16 |
| Melkhior | (plus 'self.irq.add("ps2kbd", use_loc_if_exists=True)' in the target) | 13:16 |
| tpb | Title: ## irq self.submodules.ev = EventManager() in_ctrl_31_ - Pastebin.com (at pastebin.com) | 13:16 |
| Melkhior | I can share the full code, it's a short migen wrapper around a PS2 controller from opencores.org | 13:16 |
| Melkhior | TIA for any pointer/suggestion | 13:16 |
| Melkhior | full wrapper: https://pastebin.com/GRQcnx6w | 13:20 |
| tpb | Title: ## This file is part of LiteX.## Copyright (c) 2021 Romain Dolbeau (at pastebin.com) | 13:20 |
| lkcl | _florent_: we have a practical need, litex fulfils that. however, would you consider me not at liberty to describe the experience of using litex, freely and without reserve? | 13:47 |
| lkcl | do i have to remain totally silent and self-censor if it has weaknesses and limitations? | 13:47 |
| lkcl | being up-front and honest is not "strange" to me, at all. it is a hugely valuable service, both to you and to all other litex users and developers, to know of the strengths *and* weaknesses, from the experiences of different developers | 13:49 |
| lkcl | *many people* know that litex, because it uses migen, is seriously problematic | 13:49 |
| lkcl | i am just the person that, because i have Asperger's, and because i have a policy of being absolutely honest, has talked about that publcily | 13:50 |
| lkcl | and because of that honest, you now know! | 13:50 |
| lkcl | why is this a problem? | 13:51 |
| lkcl | i would like to understand | 13:51 |
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| thorns514 | heya, I think my question yesterday got lost - I am having trouble with litescope triggers when my soc has multiple clock domains. The unit under test and the litescopeanalyzer are both in "sys", yet still, when I try to set a trigger with litescope_cli, it dumps immediately. If I remove my USB peripheral and the SoC has only one global clock, it works fine... | 14:03 |
| thorns514 | nm I see it in today's log, and I see your reply _florent_ thanks. I am setting the clock_domain to "sys" as described | 14:05 |
| thorns514 | I perhaps need to study a bit more how clocks are given to external verilog modules. I'm giving my verilog a clock via `i_clk = ClockSignal("sys")`, I presume this is the same net as the LiteScopeAnalyzer is connected to with `clock_domain = "sys"` | 14:11 |
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| lkcl | _florent_: i am serious. remember i have Asperger's, i do not play by "normal" social rules, so i choose, by default, to be simply honest and speak freely. | 14:39 |
| lkcl | is this a problem? if so, please tell me. | 14:40 |
| lkcl | i do not mind, at all. | 14:40 |
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| _florent_ | lkcl: LiteX can have weaknesses and I'm probably well more aware of them than you are, does it means it's not usable at all, not sure, and don't you see we are working on it and improving it progressively? | 15:01 |
| _florent_ | You have a binary vision: Migen = shit, nMigen = great, but this is so limited vision, don't you think there is an history behind all this, don't you think that what you can do now with nMigen would have been possible without all the work that have been done by M-Labs previously, by me, by others, etc... | 15:04 |
| _florent_ | So with you speech, you are just forgeting all this history behind which I don't think is correct for all the persons that have been involved in this and made this possible | 15:06 |
| lkcl | _florent_: i do recognise the huge amount of history and development, and all the hard work that has gone into it. to be clear: if it did not do the job, we could use it at all! the fact that it works is a huge achievement | 15:12 |
| lkcl | i have been thinking for some time, based on the weaknesses i encountered, a possible strategy for improvement. it is quite tricky, because of the amount of legacy development, so i have not spoken about it | 15:14 |
| lkcl | in the meantime, reality is what reality is. do not read anything into my honest words about difficulties i encountered during time-pressured development | 15:15 |
| lkcl | we still use it because it does the job | 15:16 |
| _florent_ | And that's why I spent time explaining why it was for now not possible to switch yet to another language, that we were working on improving the codebase, simplifying first, etc... | 15:16 |
| lkcl | ah very cool | 15:16 |
| lkcl | if you are ready / willing i have some constructive feedback there which may make addition (and development) of CPUs easier? | 15:18 |
| lkcl | it's quite a simple idea | 15:18 |
| lkcl | i would be interested to hear if you consider it practical / sound / workable / useful | 15:19 |
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| lkcl | it comes with the advantage that i'd help by implementing it :) | 15:46 |
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| _florent_ | Sorry, for now I'm tired of this discussion and don't want discuss technical things. I'd like this project/channel to be friendly and don't see why we would do an exception for you, so if you want to be welcomed here, you have to do some efforts. | 16:06 |
| _florent_ | Melkhior: nice, I'm not familiar with the interrupts in Linux, have you tried looking at the LiteEth Driver that uses the interrupts? | 16:09 |
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| Melkhior | _florent_ the linux part *should* (famous last words...) be OK, it's all standard stuff, the driver just request the 'proper' interrupt and Linux figures it out from the DTS I suppose (I basically repurposed the Altera PS/2 driver) | 16:18 |
| Melkhior | I have the right number displayed in /proc/interrupts for f0004800.ps2kbd | 16:18 |
| Melkhior | I was wondering if I could have messed up something in the design so that the interrupt would not get triggered ? Or not propagated to the PLIC/CLINT ? | 16:18 |
| Melkhior | How I could check they are triggered even if Linux doesn't see them triggering ? | 16:18 |
| Melkhior | 2: 1261625 0 0 0 SiFive PLIC 2 eth0 | 16:18 |
| Melkhior | 3: 0 0 0 0 SiFive PLIC 3 f0004800.ps2kbd | 16:18 |
| Melkhior | 5: 20872014 20880593 20880778 20880807 RISC-V INTC 5 riscv-timer | 16:18 |
| Melkhior | still could be linux itself :-( | 16:18 |
| lkcl | _florent_, ehn? i don't understand. where did you get the mistaken impression i am trying to be hostile / non-friendly from? | 16:18 |
| lkcl | i have provided a patch which improves the useability and usefulness of Litex for everyone | 16:19 |
| lkcl | here it is | 16:19 |
| lkcl | https://ftp.libre-soc.org/litex-sim-jtagremote.patch | 16:19 |
| lkcl | i have offered to help improve Litex for everyone with some simple constructive ideas | 16:20 |
| lkcl | why are you not interested in that, _florent_ ? | 16:20 |
| Finde | lkcl, he has said he doesn't want to continue the discussion here | 16:28 |
| Finde | perhaps take it up in another forum | 16:28 |
| lkcl | Finde: that's why i am confused. "does not wish to discuss contributions from willing and friendly Libre / Open Hardware Engineers" | 16:29 |
| Finde | no one is going to further engage you on this | 16:30 |
| lkcl | _florent_: which forum can be used to discuss contributions from willing and friendly Libre/Open Hardware developers, to the litex code base? | 16:30 |
| lkcl | Finde: i am completely confused as to what on earth is going on | 16:30 |
| Finde | when someone says they don't want to continue discussing something in a particular venue, I'd suggest you stop there, just as with any other conversation someone wants to end | 16:32 |
| lkcl | Finde: ah ok. Asperger's, here. sorry, i need these things spelled out, i don't understand normal conversation cues. | 16:32 |
| lkcl | understood, apologies to you both. | 16:32 |
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| sajattack[m] | _florent_: have you tried the pcie flashing on the cle-215+? I'm starting to wonder if something is different about the spiflash | 18:27 |
| sajattack[m] | reading gives all 0xFF despite having programmed something in with openocd, and trying to write fails to erase | 18:29 |
| nickoe | mmm, I wonder what has changed with litex since last time I had some time to play around with my FPGA | 18:33 |
| nickoe | that is late february | 18:34 |
| thorns514 | nickoe> I usually check the commit history on github :) | 18:34 |
| nickoe | Yeah, I will certainly glance over that! :) But maybe it is better for me to actually remember where I left off.. I mean, I know that I wanted to simulate getting stuff from SDRAM to a AIX bus somehow. | 18:37 |
| nickoe | Mmm, I thought I used vscode as an IDE, but now I remember that I used pycharm as most is python! No wonder I couldn't find my old workspace. :D | 18:38 |
| nickoe | I was looking at some litedram test cases to see if I could make the litedram to AXI stream work, but I never think I succeeded. | 18:39 |
| nickoe | hmm, "riscv64-elf-ld: Error: unable to disambiguate: -nodefaultlibs (did you mean --nodefaultlibs ?)" | 18:41 |
| nickoe | Is that really correct to have the ld have double dash options? | 18:41 |
| nickoe | mmm, I remember trying to debug https://github.com/enjoy-digital/litex/issues/831 / https://github.com/enjoy-digital/litex/issues/712 | 18:43 |
| nickoe | I whould probably dump all the hashes for the current repos and update it all! | 18:45 |
| thorns514 | oh you know what nickoe, I had that problem with verilator like a year ago, you need to fiddle with the type of the c++ function | 18:55 |
| nickoe | Maybe it is fixed with https://github.com/enjoy-digital/litex/commit/d3407c67b189d2c338766febb3bf2c57f6f80d1d | 18:56 |
| nickoe | :O | 18:56 |
| nickoe | But right now I get linker erros for the c code stuff, as above with the ld error | 18:57 |
| thorns514 | so does litex generate an entire verilator testbench for you? | 18:57 |
| nickoe | using: riscv64-elf-ld --version GNU ld (GNU Binutils) 2.36.1 | 18:57 |
| thorns514 | I always found it terribly tedious trying to write a clock properly for verilator by hand, evaluating the circuit before and after the edge etc | 18:57 |
| nickoe | Mmm, not sure, IIRC the gtkwave was not happy with the trace file | 18:58 |
| thorns514 | I wonder if I should just start doing all my designs in litex lol, even ones without a CPU, just for the infrastructure for generating sim code etc | 18:58 |
| nickoe | mm, it has the single dash here still https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/common.mak#L56 | 18:59 |
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| nickoe | mm, it is like the run target in pycharm uses another env than on my bare commandline. | 19:06 |
| nickoe | the bare commandline works | 19:06 |
| nickoe | It uses riscv64-unknown-elf-ld on the commandline but just riscv64-elf-ld in pycharm | 19:07 |
| nickoe | hmm | 19:07 |
| nickoe | ok, fixed the env for that, maybe I purely used that on the commandline last time. | 19:09 |
| nickoe | _florent_: Do you remember the donut issue I was talking about in february when simulating? | 19:10 |
| nickoe | Should I report an issue about it if it persists when I get all my stuff rebased? | 19:11 |
| nickoe | The issue bing that we seemingly only get on frame of the donut animation | 19:11 |
| nickoe | Until it returns to the primpt. | 19:11 |
| nickoe | thorns514: so do you remember how I make sure it generates a trace file? This is my simulation script, https://github.com/nickoe/litex-boards/blob/mars_ax3_sim/litex_boards/targets/mars_ax3_sim_litex.py | 19:14 |
| thorns514 | I've never done it in litex sorry, I was doing verilator by hand last year | 19:14 |
| nickoe | ok | 19:20 |
| nickoe | thorns514: Ok, so I made my old example work with https://github.com/enjoy-digital/litex/wiki/Use-LiteScope-To-Debug-A-SoC , so enabling etherbone and ethernet and using the litex server thing and the litescope cli. | 19:27 |
| nickoe | But it just dumps 1 ns of trace | 19:28 |
| nickoe | thorns514: If you used verilater directly before, do you know if one can "hot reload" traces in gtkwave? | 19:28 |
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| thorns514 | yes it's ctrl-shift-r I think ? nickoe | 20:01 |
| nickoe | thorns514: ahh, cool! I didn't notice that before, it appears to work. | 20:03 |
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| chmouss | _florent_: hi! did you had time to test the Ethernet on the Versa ECP5? | 20:10 |
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