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| Jegeva | hello hello, i am trying a first tests with litex with an arty as a target an there is something i miss, once the gatware is generated, the software compiled and all, how do i generate the bitstream for the fpga ? | 08:16 |
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| Jegeva | i range the arty?py in litex-boards/target | 08:17 |
| zyp | you run the target with --build | 08:18 |
| zyp | and you can also add --load to have it loaded | 08:18 |
| Jegeva | oh ok !! thanks, tough i would have to setup the location of vivado or something | 08:20 |
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| zyp | if it's not autodetected, you can pass that in through an environment variable | 08:35 |
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| FAFRE12 | Hello everyone, I have been trying to get litex+VexRiscV working on a zedboard. On the litex-boards repository there is a platform file for it but not a target file, I understand that this is due to the fact that the only available UART is hardwired to the PS, not to the PL. By using EMIO it is possible to make the UART available for the PL so I | 19:13 |
| FAFRE12 | created a block design where I connect VexRiscV to this forwarded UART. But when I try to "lxterm /dev/ttyACM0" I get nothing, not even the litex banner. From an issue I opened on the litex repository it seems like it is an issue with the UART itself even if it is a 115200 8ne1 UART. Does anyone know if there is a way to work around this? Or why | 19:13 |
| FAFRE12 | the UART is not compatible with litex. Thank you! | 19:13 |
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