Sunday, 2021-04-04

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thorns514trying to integrate my systemverilog peripheral into LiteX - it seems to be trying to instruct yosys to `read_systemverilog` but this command does not seem to exist?14:37
thorns514(this one builds fine standalone in yosys trellis, just trying to figure out how litex is coming up with this yosys script command)14:39
thorns514I'll make an issue to fix this, I can make a PR once I get permission from work to contribute to this project14:56
thorns514https://github.com/enjoy-digital/litex/issues/870 FYI.  Will make this a PR once I get permission, if someone hasn't just added the 6 lines themselves by then.  Thanks to all for these amazing tools, so much fun.15:10
Melkhior@_florent_ Hello, I've added a framebuffer to my SoC, currently running 640x480@60Hz (for timing).15:12
MelkhiorHowever, the display is corrupted and if I display a picture with 'fbv', everything goes to "south of heaven"15:12
MelkhiorAs far as I can tell by default nothing tells the kernel to not reuse the FB space for processes...15:12
MelkhiorIf I add a node in "reserved memory" that matches the 'reg' entry for the framebuffer node, then everything seems fine.15:12
MelkhiorDid I forgot something and the entry should be there ? Or should the kernel figure out to not reuse the same memory ?15:12
MelkhiorOr is it "normal" and the process has not yet been automated ?15:12
MelkhiorTIA15:12
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Melkhior@_florent_ BTW, if the 'add a reserved_memory' entry is by chance the proper solution I have a patch to json2dts that automates the process15:38
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cjearlsHi, I've been using some LiteX designs, like the Linux-on-LiteX-Vexriscv, for a while,  but I'm having some difficulty understanding how all the parts of litex come together or how I'd use litex to make a new design. I have an orangecrab FPGA board, and I'd like to use the microUSB port on the FPGA and some GPIO pins to act as a USB-to-UART adapter, but I'm not sure where to start. A lot of the pages that look like they'd be able to help in22:02
cjearlsthe documentation are still TODOs, so don't have any information yet22:02
cjearlsAs I learn more, I'd also be happy to help add documentation, but there are so many components and git repos and so much code that I'm having trouble finding a good starting point22:06
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