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| keesj | is there a place where the API are documented / I can link to ? | 14:16 |
|---|---|---|
| keesj | is there an example of a wishbone slave where I can act upon a wishbone write / CSR change | 14:17 |
| _florent_ | keesj: sorry not yet, the example code/wiki/projects/tutorials have to be used for that. I'd like to free up more time to do this | 14:45 |
| keesj | well. I am trying to add a little documentation to the wiki (on the adding verilog modules) but it would be nice to be able to link to the Instance documentation for example. I do a lot of grep/silversearch-ag google / search for example and ofthen that just works™ and it is all not that complicated (once you know what do do) | 14:49 |
| _florent_ | Instance are from Migen/FHDL: https://m-labs.hk/migen/manual/fhdl.html#instances | 15:00 |
| tpb | Title: The FHDL domain-specific language Migen 0.8.dev0 documentation (at m-labs.hk) | 15:00 |
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| G33KatWork | does anybody here know a good sdcard sniffing project? I looked at litesdcard, but that's master only, but I want to tap the sd commands for something and I have a hard time thinking about how to get the data properly into the fpga. The clk is async to the internal fpga clock obviously and it is also only active when there is actual traffic from the device to the sd. I don't think I can oversample the | 18:51 |
| G33KatWork | clock and command/data lines, because it's an emmc which is potentially very fast - I just don't know *how* fast yet | 18:51 |
| keesj | Just for sniffing.. Saleae Logic did work nicely for me (the pro version) emmc can be more painfull (more data lines/ ddr) (sigrok also had some code) | 18:54 |
| G33KatWork | I need it in an fpga for fault injection | 18:54 |
| G33KatWork | clk/cmd should be enough | 18:54 |
| keesj | A.. that is more my type of fun :P | 18:54 |
| G33KatWork | I am just brainstorming right now and looking for existing stuff. I didn't even prepare the hardware yet | 18:55 |
| G33KatWork | and I am not very experienced at writing my own fpga cores from scratch to be honest. talking to external components or sniffing stuff with an fpga has always been very painful to me... | 18:56 |
| keesj | I have previously worked on something like this and currently doing the same for nand flash (Mitm/TOCTOU type attacks) | 18:56 |
| keesj | is emulation an option? do you already know .. how you are going to/planning on performing the experiment on the hardware? | 18:58 |
| G33KatWork | I have something a friend did in the past - even in migen, but that was 3 years ago, I personally never used it and I am not sure if it even works flawlessly. I think it had problems with capturing the data properly | 18:58 |
| G33KatWork | emulation could work | 18:58 |
| G33KatWork | hmm, there is micah's flipsyfat: https://github.com/scanlime/flipsyfat | 19:00 |
| keesj | yes.. it no all that trivial. the more I know about it the more things are getting difficult:) and for example for serious capture you can not just sample you will probably want to clock the recived using the eMMC clock line (I used the arty serdes2 ip for that) | 19:00 |
| G33KatWork | yeah, that's exactly what I have no experience with... | 19:01 |
| G33KatWork | I guess I'm going to read some xilinx serdes appnotes then :) | 19:02 |
| keesj | hmm I had flipyfat already bookmarked but forgot about it | 19:02 |
| G33KatWork | I used it once to implement an LVDS input for a camera chip using 4x oversampling which was... quite an adventure, but I made it work in the end! (XPP523) | 19:03 |
| keesj | https://www.xilinx.com/support/documentation/application_notes/xapp1064.pdf | 19:03 |
| keesj | this works but perhaps I am overreacting :P ( I was looking at snopping ddr3 back then) | 19:04 |
| G33KatWork | haha, ouch. okay | 19:04 |
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| G33KatWork | the main thing that concerns me is that the clk might not be continous. so I need to be source-synchronous, but I don't have a continous data stream and need to lock and recover the clock more or less instantly | 19:06 |
| keesj | but that app note I think is nice but I don't know well about the latency you are allowed to have on eMMC. (SPI flash for example is quite hard to emulate) https://github.com/osresearch/spispy | 19:06 |
| G33KatWork | with every transaction the phase is going to be different etc. | 19:06 |
| keesj | The SPI protocol is difficult to emulate without specialized hardware since it has very demanding timing requirements. | 19:06 |
| G33KatWork | yeah, I remember that SPI ROM emulator trammell hudson built for SPI flash emulation. he faced the same problems | 19:08 |
| keesj | but anways.. getting the data in nicely is already great. for eMMC on startup all you need to do is give it a clock and it will spit out the data at your own rate | 19:08 |
| keesj | (the link is his work) | 19:08 |
| G33KatWork | heh, overlooked that. thanks | 19:09 |
| G33KatWork | I think I have enough to read now, thanks for the pointers! | 19:11 |
| keesj | well. it looks like you probably know your way already .. good luck and also ask other people .. I am actually a dog | 19:11 |
| G33KatWork | :D | 19:11 |
| keesj | do you publish you research somewhere? | 19:12 |
| G33KatWork | yes, I will | 19:12 |
| G33KatWork | I am not the only one working on that right now though | 19:12 |
| G33KatWork | so that somebody else I am in contact with might be faster with a different approach ;) | 19:13 |
| G33KatWork | but it's a university thesis, so I'll let him do his stuff first until he's fed up or done | 19:13 |
| keesj | we choose to use FPGA not because it is easy | 19:13 |
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| keesj | _florent_: I updated https://github.com/enjoy-digital/litex/wiki/Reuse-A-Verilog-VHDL-nMigen-Core | 19:17 |
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