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| keesj | is there an example of include some verilog code, perffably I would like a wishbone slave where I can instanciate my module | 13:40 |
|---|---|---|
| keesj | I did find litex_read_verilog (to read convert to python) but from memory there was also some "include" possibilites | 13:41 |
| acathla | keesj, find an example with something like : "platform.add_source()" | 13:50 |
| _florent_ | keesj: you have a look at: https://github.com/enjoy-digital/litex/wiki/Reuse-A-Verilog-VHDL-nMigen-Core | 14:11 |
| _florent_ | and also to some cores integrated in Betrusted, I2C for example: https://github.com/betrusted-io/gateware/blob/master/gateware/i2c/core.py | 14:12 |
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| keesj | ok nice.. and.. if I want to replace my Soc with magic python code I set cpu_type to None? | 14:29 |
| keesj | I remember also somebody being able to use the uart and debug on fomu | 14:30 |
| _florent_ | setting cpu_type=None removes the CPU from the SoC (ie you just get the SoC infrastructure) | 14:31 |
| keesj | becase the litescope adds with_etherbone but I guess there must then be a similar options for taking over the serial as wishbone master | 14:32 |
| _florent_ | yes with add_uartbone | 14:33 |
| keesj | yes, it looks like serial is still already obtained by SoCCSRHandler https://pastebin.com/1PeBgNnn even when I set the cpu type to None | 15:00 |
| tpb | Title: INFO:SoC: __ _ __ _ __ INFO:SoC: / / (_) /____ | |/_/ - Pastebin.com (at pastebin.com) | 15:00 |
| acathla | keesj, you must set : kwargs["uart_name"] = "crossover" | 15:12 |
| acathla | so your uart won't be connected to anything but accessible through wishbone reads/writes | 15:13 |
| keesj | that does produce a different result :P | 15:13 |
| acathla | and the real uart used as a wishbonebridge | 15:13 |
| keesj | https://pastebin.com/pV5yJZjL a lot of grep and code reading involved here :P | 15:15 |
| tpb | Title: INFO:SoCBusHandler:csr added as Bus Slave.INFO:SoCCSRHandler:bridge added as C - Pastebin.com (at pastebin.com) | 15:15 |
| keesj | getting hot ! | 15:17 |
| keesj | yup.. awesome... | 15:21 |
| keesj | now I need to combine this with a verilog module, nice | 15:37 |
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