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| dayjaby | nickoe I managed to get it to run in Renode (instead of lxsim). Maybe that serves its purpose for you? I documented it in https://github.com/dayjaby/litex-experiments | 00:05 |
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| _florent_ | Hi nickoe, I just made some changes to litex_sim to have the same behaviour between --ram-init and --sdram-init | 08:11 |
| _florent_ | you can now just do: | 08:11 |
| _florent_ | litex_sim --with-sdram | 08:12 |
| _florent_ | litex_bare_metal_demo --build-path=build/sim | 08:12 |
| _florent_ | litex_sim --with-sdram --sdram-init=demo.bin | 08:12 |
| _florent_ | and it will load demo.bin and jump to it | 08:13 |
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| nickoe | _florent_: Ahh cool. That does see to work now! :) | 09:21 |
| nickoe | daddesio: Also cool with the renode stuff, but can I do co-simulatio with own modules with that setup? | 09:21 |
| nickoe | _florent_: I am not sure why, but when running the donut in the simulation I only appear to get on frame before it exits back to the prompt in the app | 09:23 |
| _florent_ | nickoe: it indeeds seems to be receiving a character and exits | 09:24 |
| nickoe | Is that a bug in the serial2console module that I assume is used there. | 09:25 |
| nickoe | ? | 09:25 |
| _florent_ | This would need to be analyzed, this could be due to a \n to \n\r convertion, I'll have a closer look | 09:36 |
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| nickoe | _florent_: Why is it that the --sdram-init does not support boot.josn? It appears to be calling get_mem_data() as the parameters to SimSoC and it appers to load the files into the data that it returns. | 19:31 |
| nickoe | But sure, when I boot it appears to not boot anyting after liftoff. | 19:32 |
| nickoe | (with the skip init constant of course) | 19:42 |
| nickoe | _florent_: What is the point of the --with-analyzer on lxsim? I thought it was a replacement for https://github.com/enjoy-digital/litex/wiki/Use-LiteScope-To-Debug-A-SoC#use-the-analyzer | 19:55 |
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| nickoe | But when I run it with: "lxsim --with-sdram --sdram-init=demo.bin --gtkwave-savefile --with-analyzer" I get, https://dpaste.com/3JJSGPGLM after I interrup the simulation. | 20:01 |
| tpb | Title: dpaste: 3JJSGPGLM (at dpaste.com) | 20:01 |
| nickoe | Ok adding --trace did put stuff in the vcd file at lesat | 20:03 |
| nickoe | Why does it ask for a password when I run with --with-etherbone ? | 20:12 |
| dayjaby | Because it creates a local network interface, like tap0, which can only be done as root | 20:13 |
| dayjaby | check `ifconfig` to see the IP addresses. it should show tap0 with 192.168.1.100 and you can try to ping 192.168.1.50 (which did not work for me with lxsim tho) | 20:14 |
| nickoe | dayjaby: The guide says to use lxserer on .51, "litex_server --udp --udp-ip=192.168.1.51" | 20:26 |
| nickoe | I just tried to add the LedChaser to the sim example. | 20:26 |
| nickoe | https://github.com/nickoe/litex-boards/blob/07a7464bbc3b418e3ec4c019515e6d0fffae4530/litex_boards/targets/mars_ax3_sim_litex.py#L304 | 20:30 |
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| nickoe_ | dayjaby: you there? I feel off freenode | 20:37 |
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| dayjaby | ye, the disconnects here can get annoying :P | 20:37 |
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| nickoe_ | dayjaby: Can you example https://github.com/dayjaby/litex-experiments simulate custom hardware, such as the LedChaser as an example? | 20:39 |
| nickoe_ | And get vcd traces out? | 20:39 |
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| dayjaby | let me check | 20:39 |
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| dayjaby | appearently with something like https://github.com/antmicro/renode-verilator-integration it's possible (check https://renode.io/news/renode-verilator-hdl-co-simulation/). | 20:42 |
| tpb | Title: Co-simulating HDL models in Renode with Verilator (at renode.io) | 20:42 |
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| nickoe | dayjaby: I am not so god at the verilog simluation instrumentation thing, I mean the cpp file. So I was hoping there was a more magic way that I could use and not require me write too much spagehtti. | 20:52 |
| dayjaby | Yes, I thought the same. I've done some gdb debugging in renode, which worked well. So you need the VCD traces? | 20:53 |
| nickoe | Yeah, well. My goal is to be able to run a DSP chain in simulation that someone else is primarely working on. Then I would use the softcore with litex and the demo app or the test scripts via lxserver to poke some registers to control it. | 20:56 |
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| nickoe | I want to feed this chain with AXI DMA | 20:58 |
| nickoe | So my first goal is to be able to run this simulation where this DMA just dump data to some output signals | 20:58 |
| nickoe | but right now, I think I need to take my eyes off the screen for a bit.. I better clean up it is getting really dirty around her.e | 20:59 |
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| nickoe | by AXI DMA I mean, LiteDRAMDMAReader | 21:33 |
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| nickoe | maybe this is realated to my earlier comment about the vcd being broken as well https://github.com/enjoy-digital/litex/issues/831 | 22:36 |
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