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| tmbinc | _florent_ / G33KatWork: So ADC data is working now (https://me.elitedvb.net/s/ji2w3wzKKfypyzX; timescale is wrong of course) | 00:00 |
|---|---|---|
| tmbinc | via https://github.com/360nosc0pe/litex-boards/tree/tmbinc/work, and yes I need to clean this up etc. | 00:01 |
| tmbinc | this is CH1, and the DC offset is a bit hard to find (0x2600 constant, varies likely from scope to scope), so we need a cal tool at some point | 00:02 |
| mikeK_de1soc | Sweet!!!!! :) | 00:05 |
| mikeK_de1soc | Great Job!! | 00:05 |
| tmbinc | Thanks - actually litex made all of this easy and fun | 00:14 |
| tmbinc | _every_ single thing "just worked", 100% as expected. That is not typical for me working with FPGAs. :) | 00:15 |
| mikeK_de1soc | yes, I just my board up an running... the DE1-SoC.. not as exciting as the Scope tho... | 00:15 |
| mikeK_de1soc | do you have the display up and running? | 00:16 |
| tmbinc | We had it working in the old vivado-based design (just as a Linux framebuffer) | 00:16 |
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| mikeK_de1soc | ah ok... IS that in the files too? i wanted to check on the code, if you don;t mind. | 00:17 |
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| tmbinc | https://www.youtube.com/watch?v=l573bA7dOKY was a video of it. https://github.com/360nosc0pe/software/blob/master/cheapscope/cheapscope.py was the software (please note the glorious way of how the framebuffer works) | 00:18 |
| tmbinc | the rest of the design you can find on https://github.com/360nosc0pe/yocto and https://github.com/360nosc0pe/fpga | 00:19 |
| mikeK_de1soc | Nice!! I am at the VGA section for my "altera" board. this is where i am stuck.. | 00:20 |
| mikeK_de1soc | the vga seems to be setup for the xilinx dev tools.. not altera(intel) | 00:20 |
| mikeK_de1soc | tmbinc: I have a quick question if that's ok! Where do you call the "litex_boards/targets/sds1104xe_config.py" file from? | 00:35 |
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| dormito | As I understand it litex generates the hdl for a SoCs wishbone fabric (for projects that use wishbone). Is there a good mechanism for controlling the address of modules at run time? (especially simple special case situations, like swapping two bus maping addresses if a register bit is set) | 06:38 |
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| _florent_ | tmbinc: nice! So the next step would probably be to simplify the repository (with just the target + scripts) and add a capture datapath to upload the samples to the Host | 08:07 |
| _florent_ | tmbinc: here is a simplified version what I have in mind for a first capture datapath: | 08:08 |
| _florent_ | https://usercontent.irccloud-cdn.com/file/HMGtl0o1/SDS1104X-E_Datapath.png | 08:08 |
| _florent_ | This would allow doing large captures (with up to 20Gbps of bandwidth from the ADC) and upload slowly at 100Mbps to the Host | 08:10 |
| _florent_ | I could work on this part | 08:10 |
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| tmbinc | _florent_: sounds good. The fifo would need to handle pre-trigger capture, but essentially it's just flushing data from the beginning. | 08:43 |
| tmbinc | I can simplify the repo | 08:44 |
| _florent_ | tmbinc: ok thanks, that's just a first idea to upload the samples to the Host, we'll of course refine this. For the pre-trigger, we could add a module at the output of the FIFO that would ensure we always have the previous N samples in the FIFO (ie flush the output when more than N stored) and disable this behavior when the capture starts. | 09:06 |
| _florent_ | tmbinc: this how pre-trigger is implemented in LiteScope (but with a BlockRAM FIFO). I'm also realizing that working on this will also be useful to use a LiteDRAM FIFO with LiteScope :) (wanted to work on this for some time now). | 09:07 |
| Melkhior | _florent_ perhaps LiteX could appear in the "SoC platforms" category of https://github.com/riscv/riscv-cores-list ? (source of https://riscv.org/exchange/cores-socs/) | 09:14 |
| tpb | Title: RISC-V Exchange: Cores & SoCs - RISC-V International (at riscv.org) | 09:14 |
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| _florent_ | Melkhior: that could make sense and would probably be relevant yes, do you want to do a PR this? (just saw you have a pending PR for Vex :)) | 09:28 |
| _florent_ | The RISC-V cores currently supported are: | 09:29 |
| Melkhior | I can do the PR if it's fine with you, didn't want to jump the gun | 09:29 |
| _florent_ | - BlackParrot | 09:29 |
| _florent_ | - CV32E40P | 09:29 |
| _florent_ | - Minerva | 09:29 |
| _florent_ | - PicoRV32 | 09:29 |
| _florent_ | - Rocket | 09:29 |
| _florent_ | - SERV | 09:29 |
| Melkhior | that's one long list of cores :-) | 09:30 |
| _florent_ | - VexRiscv (SMP) | 09:30 |
| _florent_ | (and that's the end for now :)) | 09:30 |
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| Melkhior | _florent_ how do I describe the license ? That looks like BSD ? | 09:34 |
| _florent_ | yes it's BSD | 09:35 |
| Melkhior | https://github.com/rdolbeau/riscv-cores-list/commit/95917912511a4a7868bae12057660426d38f9580 works for you ? | 09:38 |
| Melkhior | _florent_ I decided against mentioning there's additional non-RISC-V cores... might not be the best place :-) | 09:42 |
| _florent_ | Melkhior: thanks, this looks good yes; I also think we should just list the RISC-V cores | 09:43 |
| Melkhior | all on your list are RISC-V I think ? (i.e. microwatt isn't in there) | 09:44 |
| Melkhior | I know most of them but not all | 09:44 |
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| _florent_ | yes I only listed the RISC-V ones | 09:45 |
| Melkhior | ok | 09:45 |
| Melkhior | thx | 09:45 |
| Melkhior | PR #67 | 09:48 |
| _florent_ | thanks! | 10:05 |
| Melkhior | _florent_ can you give an OK in the PR as enjoy-digital ? just in case they wonder why it's not the primary author doing the PR... | 10:12 |
| tmbinc | _florent_: any opinion about repo name? 360nosc0pe/scope? litex-scope? litex-sds? I want to express that it is based on litex but not part of litex, how do other FPGA-specific repos handle this? | 10:13 |
| tmbinc | https://github.com/360nosc0pe/scope for now but we can rename it | 10:23 |
| _florent_ | tmbinc: scope is a good name yes (we could still change it later if we found a better name), litex-scope would also have been a good name but is maybe too close to LiteScope so will be confusing, so scope is probably better | 10:29 |
| _florent_ | tmbinc: I'm using this font for the ASCII art on the others repos: https://patorjk.com/software/taag/#p=display&f=Small%20Slant&t=360nosc0pe | 10:31 |
| tpb | Title: Text to ASCII Art Generator (TAAG) (at patorjk.com) | 10:31 |
| _florent_ | tmbinc: but this is just a preference :), no important | 10:32 |
| _florent_ | otherwise this looks fine and will provide us a good basis to play with the scope, thanks! | 10:33 |
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| tmbinc | _florent_: fixed (the font) | 11:19 |
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| mikeK_de1soc | _florent_: I would like to submit a PR for the work that I have done on the DE1-SoC board in my tweet, (Thanks for the like btw). Again, I am not very experienced in this. I have several changes in multiple repositories. Do I submit each one individually, and you review each one? Also, I started to add the support for the Framebuffer for the | 13:33 |
| mikeK_de1soc | Cyclone5 devices. But currently it's not working yet. Did you want me ignore those at the moment? Currently the build will pass because I have the Frame buffer ignored in make.py makefile. Thanks! MikeK | 13:33 |
| _florent_ | mikeK_de1soc: yes, you could create PRs for the parts that have been validated, for the framebuffer, we can wait to have something working before integrating. | 13:36 |
| mikeK_de1soc | ok will do! | 13:36 |
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| tmbinc | mikeK_de1soc: sorry, missed your question yesterday - the script is executed manually. (It moved to https://github.com/360nosc0pe/scope/blob/main/software/sds1104xe_config.py now) | 14:34 |
| mikeK_de1soc | Thanks! :) | 14:35 |
| mikeK_de1soc | Sorry, After a quick look through your documentation, i could not find how big the FPGA is? still looking.. | 14:44 |
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| tmbinc | it's a xc7z020 | 14:49 |
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| mikeK_de1soc | ok thanks... | 15:05 |
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| Melkhior | darn, the micro-sd card now won't work even in SMP VexRiscv BIOS, the one place it was reliable :-( | 17:34 |
| Melkhior | updated everything, not sure what it could be ... previous update was done not that long ago but can't remember the exact date (definitely after Feb 4 from repos that were changed then and not since. | 17:34 |
| Melkhior | tried rolling back litex but didn't seem to fix (not sure I did the rollback properly...) | 17:34 |
| Melkhior | any idea which repo I should look at ? | 17:35 |
| nickoe | Melkhior: mm, how do you "update"? | 17:47 |
| Melkhior | python3 litex_setup.py --user update | 17:48 |
| Melkhior | in the top level, so that updates everything | 17:48 |
| Melkhior | I've rolled back litedram, and I now have a as-yet-unseen failure mode: the BIOS fails to load boot.json (standard), but instead of failing straight away at loading boot.bin it loads some of it ... and then stops. never seen that before... | 17:50 |
| nickoe | Ok, I don't konw. I am new to the litex ecosystem or whatever you call it, but sdcard via SPI works for me on my custom board. But I installed a week or two ago. | 17:50 |
| Melkhior | My hardware & sd-card have a long history of being a major nuisance:-) it works to load files (worked, past tense now) in Linux-onLitex-VexRicsv BIOS (UP or SMP), it can read data in LInux SMP, read corrupted dat ain Linux UP, and won't load anything in Linux-on-Litex-Rocket at the BIOS ... all of that in SD mode ; SPI mode has never worked with | 17:53 |
| Melkhior | LiteX or with my own project unrelated to LiteX with a couple of SPI sd-card controller from GitHub... | 17:53 |
| Melkhior | it's weird | 17:53 |
| Melkhior | but oh well :-) | 17:54 |
| Melkhior | Loading data from the BIOS was my primary use case in Litex so as it worked I thought I could ignore the problem... and not it doesn't work anymore:-) | 17:54 |
| Melkhior | well, I know what to took at this week-end now! | 17:55 |
| mikeK_de1soc | Hi Melkhior: Just wanted to let you know my RiscV is working on my De1-Soc!! Gave you Kudo's in my tweet!!! | 18:05 |
| mikeK_de1soc | Thanks for All your help yesterday!! | 18:05 |
| Melkhior | mikeK_de1soc cool & glad I could be helpful! | 18:06 |
| mikeK_de1soc | yeah absolutly,, Just letting you know I upped my serial to 203400 kbs, twice as fast as 115.2 and it worked! great tip on recompiling the fpga core.. that was great! | 18:07 |
| mikeK_de1soc | yeah, i found doing a litex-setup --user setup did not work too well for me either. Could you use a different branch of Github? and do things this way? just an idea. | 18:08 |
| Melkhior | just trying to rollback repo that could be relevant one by one... worse case scenario I can do like last time i had update issue: create a new user in the VM and starts from scratch to make sure I have a clean slate :-) | 18:10 |
| mikeK_de1soc | Wah.... and this is All from litex XXX repo's? there must be a better way... | 18:14 |
| Melkhior | well I rolled back litesdcard and that solved the problem (also rolled back litex & litedram) ; so I guess this week-end i'll have to do some bisecting to figure out the actual issue ... | 18:18 |
| Melkhior | got to go | 18:19 |
| Melkhior | bye :-) | 18:19 |
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| nickoe | Melkhior: well, what commits work and what not? Related to https://github.com/enjoy-digital/litesdcard/issues/22 ? | 21:33 |
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