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| futarisIRCcloud | https://lca2021.linux.org.au/schedule/presentation/110 in 5 mins | 03:21 |
|---|---|---|
| tpb | Title: linux.conf.au 2021 | Presentation: Open Source FPGA Tooling, Our Journey from Resistance to Adoption (at lca2021.linux.org.au) | 03:21 |
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| geertu | cr1901_modern: default config, OrangeCrab r0.2 | 10:25 |
| geertu | never saw the SDRAM init issues on mine | 10:25 |
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| andrewb1999 | Is there a way to easily do clock domain crossing for AXI-lite in liteX? | 17:59 |
| andrewb1999 | I want to connect to an axi-lite module that needs to run slower than the main SoC itself | 18:00 |
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