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| acathla | Any advice on how to get wishbone-tool work on a versa-ecp5 through ethernet? I don't even know which ethernet port is the default. | 10:09 |
|---|---|---|
| acathla | I ran : ./versa_ecp5.py --device=LFE5UM --load --csr-csv csr.csv --with-etherbone --eth-ip 192.168.52.1 --build | 10:10 |
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| acathla | Oh, does --eth-phy select the port? | 10:12 |
| acathla | it does | 10:18 |
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| somlo_ | wish the nexys4ddr had two ethernet ports... too bad --with-etherbone and --with-ethernet are mutually exclusive :) | 15:53 |
| daveshah | there might be an ethernet pmod around? | 15:59 |
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| daveshah | (*not* the NIC100 thats some silly SPI ethernet thing, but I'm sure I've seen a proper RMII or similar one before) | 15:59 |
| somlo_ | thanks! (honestly, in retrospect I feel like I should have been able to come up with that idea *eventually*) -- but I'm not in a very sharp frame of mind right now :D | 16:05 |
| somlo_ | I'll order a pmod and do some hacking, should make for a much less painful litescope debugging experience... | 16:06 |
| daveshah | looks like there are some LAN8720 modules out there that should work with liteeth | 16:06 |
| daveshah | don't know if anyone has actually tested one yet though | 16:06 |
| daveshah | https://www.amazon.co.uk/Waveshare-performance-LAN8720-Board-Transceiver/dp/B00N4JW3YK | 16:06 |
| somlo_ | daveshah: thanks! I think the US-ified amazon link would be https://www.amazon.com/Waveshare-performance-LAN8720-Board-Transceiver/dp/B00N4JW3YK | 16:10 |
| somlo_ | looks like the exact same thing, hopefully | 16:10 |
| daveshah | yep | 16:10 |
| somlo_ | ordering now... (thanks again!) | 16:11 |
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| _florent_ | somlo_: that's not integrated in the targets, but you can use the hybrid mode of LiteEthMAC for that: https://github.com/enjoy-digital/litex/blob/master/litex/tools/litex_sim.py#L224-L248 | 17:02 |
| _florent_ | somlo_: but using an additional PMOD is also a nice way to decouple things/issues. | 17:03 |
| somlo_ | _florent_: I'll check out the hybrid mode (one already has to modify the target files to instrument them for litescope, so a bit more hackery while at it should be ok) | 17:32 |
| somlo_ | it's just that I have a lot of moving parts (bitstream changes x kernel sdcard driver changes) and not having netboot capabilities leads to lots of plugging and unplugging of the sdcard to copy updated boot.bin images to it... Wanted to streamline my workflow before I really dive in and test my new-found skills with litescope :D | 17:34 |
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| _florent_ | somlo_: sure :), also if that can be useful: LiteScope can also be run over UART | 18:33 |
| acathla | _florent_, right, but can you run litex_term while litescope is running, on the same uart with crossover? | 18:37 |
| acathla | I couldn't find how | 18:38 |
| _florent_ | acathla: yes it's possible | 18:38 |
| _florent_ | litex_server --uart --uart-port=/dev/ttyUSBX | 18:39 |
| _florent_ | then litex_term crossover | 18:39 |
| acathla | but the port is already opened by litex_server for the litexscope thing | 18:40 |
| acathla | I'll try again soon... | 18:40 |
| _florent_ | litex_server accepts multiple clients | 18:40 |
| acathla | litex_term can use litex_server? | 18:41 |
| _florent_ | that's very useful to avoid mixing things in scripts :) | 18:41 |
| _florent_ | it's recent but yes | 18:41 |
| somlo_ | _florent_: can I keep using "screen /dev/ttyUSBX" or do I have to use litex_term via litex_server to access the console ? | 18:42 |
| somlo_ | i.e., will there be an additional /dev/ttyUSBXYZ device for litescope debugging, or (probably this, since you already mentioned multiplexing) it's all multiplexed over the same serial link (console *and* litescope transfers) ? | 18:42 |
| _florent_ | somlo_: in you case I was suggesting adding a second UART dedicated to the bridge (through a PMOD) | 18:42 |
| somlo_ | ah | 18:43 |
| somlo_ | so I'll need extra pmod hardware either way | 18:43 |
| _florent_ | just that it's probably easier than adding a second ethernet | 18:43 |
| somlo_ | have a (link to) a component handy? The ethernet pmod thing I ordered shows delivery by mid-February, so maybe I can find a pmod-uart thing that ships faster, and use whichever one I get first :) | 18:44 |
| daveshah | https://www.mouser.co.uk/ProductDetail/Digilent/410-212?qs=s%2FdyVPQMB4wcQVUQRTwfoQ==&mgh=1&vip=1&gclid=CjwKCAiAo5qABhBdEiwAOtGmbiv4WLlkHAoIOZ-_QarRJtI_-ZAqbSp4G24KS_KFPRDge5yQWpXyLxoCWA8QAvD_BwE | 18:44 |
| daveshah | is a PMOD UART I've used before | 18:45 |
| somlo_ | daveshah: thanks! | 18:45 |
| daveshah | also at digikey et al. | 18:45 |
| _florent_ | it's just a matter of adding a debug_serial to the platform and doing in your SoC: self.add_uartbone("debug_serial", sys_clk_freq) | 18:45 |
| _florent_ | and you have a debug bridge that can communicate with litex_server --uart --uart-port=/dev/ttyUSBX | 18:46 |
| acathla | https://github.com/enjoy-digital/litex/wiki/Use-Host-Bridge-to-control-debug-a-SoC#add-a-uart-bridge-to-your-soc | 18:47 |
| somlo_ | acathla: I remember now seeing that and ignoring it, I was on a mission to set it up over ethernet :) | 18:51 |
| somlo_ | but yeah, digikey stuff is likely to win the shipping race, so I'll likely end up using the uart method for "real" debugging :) | 18:51 |
| _florent_ | somlo_: ah another option: generate your SoC with uart_name=jtag_uart, then use litex_term jtag_uart and use the default serial for uartbone, does not require an additional PMOD :) | 18:55 |
| somlo_ | so that would be multiplexing the console and litescope data over the same serial link? | 19:07 |
| Zguig | Hi all, trying to understand and use litex, here are some questions I have: | 19:08 |
| Zguig | 1. When I start the sim.py of linux-on-litex-vexriscv, with prebuild stuff, my Linux boot "hangs" at "[ 0.014830] sched_clock: 64 bits at 1000kHz, resolution 1000ns, wraps every 2199023255500ns". I waited some quite long time for me. Shoudl I just be patient and wait for hours? | 19:08 |
| Zguig | 2. When I try to generate the bitstream for ecpix5 board (./make.py --board=ecpix5 --cpu-count=1 --build), I always got a timing issue with 1 path: Warning: Max frequency for clock '$glbnet$sdrio_clk': 69.76 MHz (FAIL at 75.01 MHz). Max I could get is 71MHz. Is it a known issue? Should I just ignore the warning and program the board? | 19:08 |
| Zguig | 3. Do you have any tutorial for implementing a custom core to advice? I want to rewrite and finalize this project I worked some time ago and was passing more time to fight with or1k stuff than working on the added value I have. Basically, I want to do a wishbone controlled generic RX/TX. There are some functions written in VHDL that I want to port to litex (and some new to be done/finished).The closest example I could find is the liteth core. | 19:08 |
| Zguig | https://github.com/euryecetelecom/euryspace/tree/master/hw/rtl/ccsds_rxtx | 19:08 |
| somlo_ | oh wait, do I already have two serial devices in play over the same serial cable (the jtag used to program the board, and the "regular" serial console uart)? And here I'd be re-using the jtag for actual console i/o, and the "normal" serial uart for litescope purposes? | 19:09 |
| somlo_ | wonder what changes I'd have to make to the DT to get BBL and linux to play along (probably reflected in the csr.csv file) | 19:10 |
| acathla | somlo_, what's your board? | 19:11 |
| somlo_ | nexys4ddr | 19:12 |
| somlo_ | I have /dev/ttyUSB0 (presumably the jtag), and I use console over /dev/ttyUSB1 | 19:12 |
| acathla | On a versa_ecp5 there are ttyUSB0 and USB1, USB0 disappear after FPGA being configure, and USB1 as console too | 19:12 |
| somlo_ | guess what _florent_ suggested is to *reuse* /dev/ttyUSB0 (jtag) for the console, and dedicate the "regular" uart to litescope/uart-bone | 19:13 |
| acathla | cool | 19:13 |
| somlo_ | acathla: sadly my stuff won't fit on a versa (rocket chip with mmu to run "real" linux) | 19:13 |
| acathla | because I failed at using ethernet | 19:13 |
| somlo_ | I can barely fit a non-MMU bare-metal-only rocket on the versa | 19:13 |
| acathla | Wow. I try to use a versa_ecp5 because my design + debug is too big for an iCE40up5K :) | 19:14 |
| somlo_ | ethernet works great (for litescope) on the nexys, but that in turn means I can't netboot the kernel, which means I have to screw around moving the microSD card back and forth between the board and my laptop to update the kernel+bbl I'm trying to boot and debug, in conjunction with the bitstream/gateware I'm *also* trying to debug at the same time :) | 19:17 |
| acathla | nexys4ddr Logic Slices : 15,850 (4 6-input LUTs & | 19:17 |
| acathla | 8 flip-flops each) | 19:17 |
| acathla | Is that big? | 19:17 |
| somlo_ | It's significantly bigger than the 45k ecp5 (or even the 85k ecp5). Rough guesstimate is that I can fit about three times as much "gateware" on the artix7 provisioned on the nexys (with vivado) as I can fit stuff on the 85k ecp5 (with yosys/trellis/nextpnr) | 19:19 |
| somlo_ | and I know that because the fpu-less rocket soc occupies about 80% of the ecp5-85k, and the fpu is about twice as big as everything else, and I can fit the fpu-in-gateware based rocket on the nexys | 19:20 |
| somlo_ | I'm really not qualified to be saying all this stuff though, I never really sat down to do a systematic study of how much logic I can fit on each type of chip :) | 19:20 |
| somlo_ | acathla: btw, it's called the "nexys a7" these days (should be compatible and/or functionally identical to the nexys4ddr): https://store.digilentinc.com/nexys-a7-fpga-trainer-board-recommended-for-ece-curriculum/ | 19:23 |
| tpb | Title: Nexys A7 Artix-7 FPGA Trainer Board - Digilent (at store.digilentinc.com) | 19:23 |
| somlo_ | I think I have the A7-100T version (of the older nexys4ddr board), i.e. the one with the larger capacity | 19:25 |
| somlo_ | or maybe that was the only kind of nexys4ddr, and now the a7 has a "cheap" option that's new, I don't really know for sure... | 19:26 |
| acathla | Oh, ok, A7-100 means it's the equivalent of 100 old style cells | 19:34 |
| acathla | _florent_, that's nice, "litex_term crossover" uses directly the running litex_server. It would be nice if it was visible with --help option. | 19:44 |
| acathla | And it's faster than wishbone-tool -s terminal | 19:45 |
| _florent_ | Zguig: Hi, it seems the simulation is indeed not going to the Linux prompt: | 20:32 |
| _florent_ | https://github.com/litex-hub/linux-on-litex-vexriscv/issues/186 | 20:32 |
| _florent_ | I'll have a look, it could be related to the clock frequencies passed in the .dts | 20:34 |
| _florent_ | for the ecpix5, I don't remember the timings results, but you can try to lower the clock or disable SDCard/Ethernet if you want more margin | 20:35 |
| _florent_ | we don't have yet a tutorial to integrate a custom core, but Betrusted is a good example project for that | 20:36 |
| _florent_ | for example: | 20:37 |
| _florent_ | https://github.com/betrusted-io/gateware/tree/master/gateware/i2c | 20:37 |
| _florent_ | or | 20:37 |
| _florent_ | https://github.com/betrusted-io/gateware/tree/master/gateware/sha512 | 20:37 |
| _florent_ | somlo_: yes I was suggesting reusing /dev/ttyUSB0 (JTAG) as a JTAG UART | 20:38 |
| cr1901_modern | _florent_: Will you be around in 5 minutes? I had an error w/ linux-on-litex that I don't understan | 20:39 |
| cr1901_modern | but I need to rerun it to get the error | 20:39 |
| _florent_ | somlo_: the only change required to your SoC is passing --uart-name=jtag_uart and then use litex_term jtag_uart (and have OpenOCD installed) | 20:40 |
| _florent_ | cr1901_modern: Hi, yes I'll be around | 20:42 |
| cr1901_modern | Awesome I'm building now... as soon as device-tree-compiler installs | 20:43 |
| cr1901_modern | (is this a new dep? Don't seem to remember that last I built) | 20:43 |
| cr1901_modern | HeAP Placer Time: 32.10s Wow, that's the longest I've ever seen nextpnr take. It must be working | 20:47 |
| cr1901_modern | (If daveshah sees this: I'm not being too serious. Still pretty fast.) | 20:47 |
| cr1901_modern | _florent_: Okay, I can't duplicate the error this time around. And I found the original error: http://ix.io/2KBL | 20:51 |
| cr1901_modern | This was with "python3 make.py --board orangecrab --build" on Dec 31st. Seems in the past 3 weeks whatever bug I saw is gone. | 20:52 |
| cr1901_modern | Now gonna upload the firmware/see what happens | 20:52 |
| somlo_ | _florent_: haven't yet used litex_term -- is it a wrapper around openocd, and if so, am I supposed to program the board through it as well as access the console, or is that a separate (direct) openocd command as I've been using it so far (with console on ttyUSB1)? | 20:52 |
| cr1901_modern | somlo_: litex_term is a terminal app like minicom | 20:54 |
| cr1901_modern | the reason you use it to program boards is that litex BIOS looks for a special ASCII string that tells the BIOS to send a binary over the serial port | 20:54 |
| cr1901_modern | and litex_term knows how to send that special ASCII string to commence programming | 20:54 |
| cr1901_modern | (it's a string that a user is very unlikely to type themselves) | 20:55 |
| somlo_ | cr1901_modern: ok, so I would *not* use it to program the board's *bitstream*, only software as an *alternative* to sdcard/tftp boot, etc. | 20:55 |
| cr1901_modern | Yes | 20:55 |
| cr1901_modern | Every board that litex supports should support that boot mode (send over serial) | 20:56 |
| somlo_ | what confused me was _florent_'s suggestion to use it with the `port` argument set to "jtag" and the "need to have openocd installed" | 20:56 |
| cr1901_modern | I'm not familiar w/ using openocd w/ jtag, so I'm not sure what _florent_ means there | 20:56 |
| somlo_ | I'm supposed to use console-over-jtag to free up my "regular" uart for litescope debugging | 20:56 |
| cr1901_modern | err sorry, not familiar w/ litex and openocd* | 20:56 |
| cr1901_modern | Oh, it might be possible to send UART traffic over the JTAG port | 20:57 |
| Zguig | Hi _florent_, thanks for your feedbacks. Regarding to my last question (an example advice), the TX part was semi-functional and all the RX has to be done. I have to admit that VHDL writing makes me going a bit crazy/with headaches... So I search more an example to write from scratch a litex core (and not encapsulate the existing one like the betrusted project did). | 20:57 |
| cr1901_modern | and litex_term knows how to connect to openocd as well | 20:57 |
| cr1901_modern | to interpret UART traffic sent over the JTAG port | 20:58 |
| cr1901_modern | but even in that case, you're _not_ using litex_term to program the bitstream | 20:58 |
| somlo_ | and my obvious attempt to connect `screen /dev/ttyUSB0` (i.e., the jtag device) instead of the "regular" ttyusb1 (the "usual" serial port) didn't work, so I'm assuming there's some magic serial-over-jtag encapsulation that a regular minicom/screen/whatever terminal program wouldn't be capable of | 20:58 |
| cr1901_modern | Correct- that "magic" is what litex_term will be doing I think. Nothing prevents someone from adding it to other terminal programs | 20:59 |
| cr1901_modern | I started adding serial boot to another terminal, but am holding off on that project for now | 20:59 |
| somlo_ | right, so I am openocd-ing the bitstream as before; then, I'm using litex-term to drive openocd to tunnel serial traffic to the "jtag uart" :) | 20:59 |
| cr1901_modern | yes | 21:00 |
| somlo_ | cr1901_modern: ok, that makes sense -- just trying to mentally place all the moving parts into their rightful little boxes :) | 21:00 |
| somlo_ | thanks! | 21:00 |
| cr1901_modern | Yw | 21:00 |
| cr1901_modern | Now if you're running into issues w/ using UART-over-JTAG, well I've never used that, so I don't think I can help :P. | 21:02 |
| somlo_ | then I'll wait for the digikey shipment of my external 2nd (pmod) uart :D | 21:02 |
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| cr1901_modern | _florent_: This doesn't seem good: http://ix.io/2MCo | 21:57 |
| cr1901_modern | What might be causing this (orangecrab, default settings) | 21:57 |
| somlo | _florent_: after programming a "--uart-name jtag_uart" bitstream to the nexys4ddr board, it appears to wait until I connect with "litex_term jtag_uart" before it starts the self-test and boot sequence | 22:11 |
| somlo | is that expected? | 22:11 |
| somlo | otherwise looks like it's working OK, now on to bridging litescope over the "regular" uart | 22:12 |
| acathla | somlo, I have the same behaviour with a normal uart | 22:15 |
| cr1901_modern | I would say that's expected- the firmware stops while the transmit buffer is full | 22:16 |
| cr1901_modern | and the banner will certainly take up the buffer | 22:17 |
| somlo | I *think* I remember it progressing independently with the normal uart, but then again, I usually had that open in screen or minicom | 22:59 |
| somlo | I seem to remember that, if I did NOT have minicom open right during/after the openocd bitstream push, I'd later find it fully booted, at the linux busybox prompt | 22:59 |
| somlo | now with the jtag uart, if I connect to it 20 minutes after pushing the bitstream with openod, it starts booting right then and there, clearly having waited for me | 23:00 |
| somlo | not a problem, just different from what (I think) I saw before | 23:01 |
| somlo | but so far so good, I now have an open UART to try to use for litescope. | 23:02 |
| cr1901_modern | _florent_: For some reason when I reset my board when UART_POLLING is not defined _and_ I'm using a USB uart, the UART stops receiving characters properly (transmitting unaffected). Is this a known bug? | 23:05 |
| cr1901_modern | somlo: Maybe you can teach me something... is JTAG UART a separate second UART you attach to a litex design? | 23:33 |
| cr1901_modern | IIRC, add_uart() in soc.py is sugar for manually adding a UART that the BIOS expects to exist. If you add a second UART for debugging the first UART, as is my intent, I'm on my own lmao | 23:35 |
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| zyp | somlo, I figure the normal uart doesn't have flow control, so it'll just transmit regardless of whether anybody is listening or not | 23:47 |
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