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| futarisIRCcloud | palmer: Did someone point you at a way to run rv32 linux in a simulator? https://github.com/litex-hub/linux-on-litex-vexriscv - follow the README and ./sim.py ... | 01:18 |
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| acathla | How do I captures signals with LiteScope that are in submodules from the main soc module ? And all those signals that are not self.something ? Since it's all flat in the end in Verilog those should all be accessible. | 09:37 |
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| hansfbaier | acathla: I am interested in this too. Probably shoud go into the wiki page | 10:01 |
| acathla | hansfbaier, yes. The Wiki says: Note: LiteScope also accepts Migen's Records, but it gives me an error when I try : TypeError: object of type 'UART' has no len() | 10:20 |
| hansfbaier | acathla: I usually set a breakpoint there and inspect the object and look inside for Signal type objects | 10:25 |
| hansfbaier | But that won´t work with Verilog code | 10:25 |
| zyp | acathla, I'm not sure there's any reasonable way to get access to signals that are not exposed, I just change the module to expose them | 10:30 |
| acathla | Ok. So soc.cpu.ibus but not all the other modules? | 10:45 |
| acathla | Like an UART | 10:45 |
| acathla | Oh, it needs a Record() | 10:47 |
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| acathla | litescope_cli.py at line 115 calls RemoteClient() with no option, expecting the csr.csv file to be in the same folder, and not in a build folder. | 15:49 |
| Guillaume14 | Hi Guys, sorry to disturb, was wanting to give a try to litex and followed the linux-on-litex-vexriscv project / readme. Sadly, I got this message when starting the sim: | 15:51 |
| Guillaume14 | INFO:SoCCSRHandler:supervisor CSR allocated at Location 5. | 15:51 |
| Guillaume14 | Traceback (most recent call last): | 15:51 |
| Guillaume14 | File "/home/grembert/Research/litex/linux-on-litex-vexriscv/./sim.py", line 226, in <module> | 15:51 |
| Guillaume14 | main() | 15:51 |
| Guillaume14 | File "/home/grembert/Research/litex/linux-on-litex-vexriscv/./sim.py", line 199, in main | 15:51 |
| Guillaume14 | soc = SoCLinux( i!=0, | 15:51 |
| Guillaume14 | File "/home/grembert/Research/litex/linux-on-litex-vexriscv/./sim.py", line 131, in __init__ | 15:51 |
| Guillaume14 | phy_settings = get_sdram_phy_settings( | 15:51 |
| Guillaume14 | File "/usr/lib/python3.9/site-packages/litex/tools/litex_sim.py", line 152, in get_sdram_phy_settings | 15:51 |
| Guillaume14 | return PhySettings( | 15:51 |
| Guillaume14 | TypeError: __init__() got an unexpected keyword argument 'rdcmdphase' | 15:51 |
| Guillaume14 | I am on Manjaro/Arch linux, and I used packages from the AUR repo | 15:51 |
| Guillaume14 | Any idea what is going on for me? Am I missing some installation dependencies? | 15:52 |
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| _florent_ | Hi Guillaume14, can you try installing the upstream repositories by following the installation guide?: https://github.com/enjoy-digital/litex/wiki/Installation | 16:57 |
| _florent_ | linux-on-litex-vexriscv uses upstream repositories | 17:00 |
| Guillaume14 | Hi _florent_, thanks for your feedback, you are right, I thought that it would be more "bug-free" to use packaged versions and didn't followed this part of the readme... My fault!! I pass this stage now. Thanks a lot, I can continue my investigations to understand a bit how this promising project works! | 17:10 |
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