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| somlo | _florent_: thanks, that took care of it! With that out of the way, any objections to https://github.com/litex-hub/litex-boards/pull/144 ? | 00:19 |
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| hansfbaier | Does anyone know about an example of using a nmigen-based core in litex. I looked at the minerva cpu example, but that seems to be quite different from a regular core.... | 05:46 |
| hansfbaier | Also I didn't find much googling | 05:46 |
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| _florent_ | hansfbaier: to integrate a nmigen-based core you can generate it as verilog and then just use instance and add the sources to the platform, as done for example here with a verilog core: https://github.com/betrusted-io/gateware/blob/master/gateware/i2c/core.py#L106-L132 | 07:56 |
| hansfbaier | _florent_: Thank you so much, that's what I was looking for (I digged through the lab examples, it had the platform.add_source() call, but was missing the verilog file, so I could not get a complete picture from that) | 08:05 |
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| hansfbaier | _florent_: I will fill in the wiki page once I get it working | 08:29 |
| _florent_ | hansfbaier: starting filling https://github.com/enjoy-digital/litex/wiki/Add-A-Verilog-VHDL-Core could be useful yes (we could rename it to Add-A-Verilog-VHDL-nMigen-Core later) | 08:30 |
| hansfbaier | _florent_: Yes, I saw that page. Will do. | 08:35 |
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| somlo | _florent_: I can now get 100MHz with rocket (linuxq variant, 256 wide litedram connection), ethernet, and litesdcard on genesys2 | 15:33 |
| somlo | now I need to find out how much additional gateware I can stuff in: non-emulated FPU, multi-core, etc. | 15:35 |
| somlo | and of course test on the actual board :) | 15:35 |
| zyp | nice | 15:56 |
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| somlo | turns out I can get a quad-core, "hard" FPU Rocket cpu with litex to pass timing at 100MHz, and LUT utilization is 58.96% | 22:35 |
| somlo | now I *have* to go grab my board and see this thing in action! | 22:36 |
| somlo | for context, this is on a genesys2 board | 22:36 |
| daveshah | Wow nice | 22:36 |
| daveshah | I didn't know we even had multi core Rocket support yet | 22:37 |
| somlo | daveshah: it's the same AXI interface to litedram, mmio, and dma-slave as any other rocket | 22:37 |
| somlo | might be a bit fiddly w.r.t. the device tree table, but I'll find out soon enough | 22:38 |
| somlo | the Rocket is sort-of its own SoC, with internal L1, interrupt controllers, etc. | 22:39 |
| somlo | the cache coherency is (well, "should be") handled internally, so there's nothing for us LiteX folks to worry about | 22:39 |
| somlo | again, in theory - I've just been building bitstreams to test for timing and utilization, haven't actually run into any "in practice" brick walls yet :) | 22:40 |
| daveshah | Yeah, I wonder if the LiteX init code will need changing to do something with the other harts too | 22:41 |
| daveshah | I guess whatever works for smp vexriscv would work for smp rocket too there | 22:41 |
| somlo | daveshah: probably... | 22:42 |
| daveshah | If you're very patient it should be possible to test that in sim :) | 22:42 |
| somlo | for now, here's the only as-of-yet unpublished portion -- patch against pythondata_cpu_rocket: https://pastebin.com/R3bwgQUD | 22:42 |
| tpb | Title: diff --git a/pythondata_cpu_rocket/verilog/update.sh b/pythondata_cpu_rocket/ver - Pastebin.com (at pastebin.com) | 22:42 |
| somlo | daveshah: I'm going to try to drop by the office later this evening (somewhat less painful process to get in and out) and grab the board; then tomorrow I can hit that brick wall (likely before any sim I'd start right now would get anywhere useful :D) | 22:44 |
| somlo | blah, obviously there's another unpublished bit (using that quad/fpu-enabled variant in litex itself): https://pastebin.com/Bh0crNQA | 22:46 |
| tpb | Title: diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/cor - Pastebin.com (at pastebin.com) | 22:46 |
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