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| disasm[m] | Sorry for maybe a recurring question. Can anyone tell me how to pronounce "Migen" and "LiteX" correctly? | 10:35 |
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| daveshah | somlo: that commit that causes things to consistently fail is https://github.com/YosysHQ/yosys/commit/9a4f420b4b8285bd05181b6988c35ce45e3c979a; now I am trying to figure out if the opt_dff move actually broke something or just triggered some broken behaviour elsewhere | 12:54 |
| _florent_ | disasm[m]: Migen is the short the abbreviation of Milkymist generator, so Mi - gen | 14:57 |
| _florent_ | LiteX is pronounced Lite - X | 14:57 |
| disasm[m] | _florent_: thanks! | 15:17 |
| somlo | daveshah: thanks! -- fingers crossed it's not too horrible to fix... | 15:25 |
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| daveshah | rocket is such a PITA to debug I don't know, I have spent the whole day looking at it and made little progress | 16:15 |
| daveshah | ideally something that is not such a mess will also hit the same bug and be easier to debug | 16:16 |
| daveshah | OK, when adding -flatten to synth_xilinx to make the first stages of synthesis the same as ECP5, it seems to fail in the same way (with Vivado PnR) | 18:57 |
| daveshah | Makes sense as that commit was mostly changing generic stuff | 18:57 |
| somlo | daveshah: I like rocket from a "dumb downstream user" standpoint -- feature-complete rv64gc. Pity it's so "outsider-resistant": I did the chisel tutorial and comprehended most of it at the time, but then I try to look at the sources of Rocket, and it takes hours and days to figure out how the simplest things are conected :( | 20:57 |
| daveshah | wait until you look at the generated Verilog... | 20:57 |
| somlo | I have, and the only marginally comprehensive thing is to follow the module interfaces to try to reverse engineer some of the "schematics"; the body of each module is practically line noise... | 20:59 |
| Finde | I'm a little surprised no one's got ariane into litex | 21:00 |
| somlo | back about two years ago, I needed a linux-capable rv64gc core in litex, and I remember looking at both, and rocket won because it appeared more mature. Being a "dumb downstream user" like I said earlier, I wanted the cheapest (in terms of my own brain cell expenditure) way of getting 64-bit linux working on litex :) | 21:03 |
| somlo | side rant: I know lots of people who know a thing or two about digital design like to trash-talk Verilog, just like a lot of modern software types like to trash-talk C; to me, both have the same main quality, of allowing an outsider to follow the "design thread" of something written in either, with comparative ease | 21:06 |
| daveshah | I actually don't have a problem with higher level HDLs per se, just Chisel's output tends to be particularly impenetrable | 21:07 |
| somlo | unlike the cool OOP-style languages (chisel for HDL, all the go/rust/whatever on the software side) where figuring out what's going on is made harder for any outsider by virtue of OOP's wherever you're looking, what you seek happens somewhere completely different style of source layout :) | 21:08 |
| somlo | I get that chisel treats verilog the way high-level software languages treat raw binary opcodes :) | 21:09 |
| daveshah | It just seems to generate some particularly strange patterns | 21:09 |
| somlo | and they don't want you looking at the verilog to troubleshoot what's wrong with it, at least not from what I remember from the official party line :) | 21:09 |
| daveshah | I find both Migen and nMigen a lot easier to debug than Chisel - little different to debugging Verilog tbh | 21:10 |
| daveshah | hard to avoid looking at the verilog when debugging the synthesis tool though ;) | 21:10 |
| somlo | to me, [n]Migen is like a Python-augmented "generate-on-steroids" verilog enhancement | 21:11 |
| daveshah | Yeah | 21:12 |
| somlo | whereas Chisel is to Verilog like Haskell is to assembly opcodes :D | 21:12 |
| daveshah | I personally prefer that, but I may be a biased perspective because I spend most of my life debugging toolchains rather than writing HDL | 21:12 |
| daveshah | so arguably not the typical end user of these thigns | 21:12 |
| somlo | that's my whole point (in defense of C and verilog, against the language-ninja trend of the current times) | 21:13 |
| somlo | when shit hits the fan, it's just less painful to figure out what's going on :) | 21:13 |
| somlo | and this whole conversation reminds me, I haven't updated Litex's rocket verilog in a good number of months either, wonder what will happen when I do that... | 21:19 |
| daveshah | I was playing around with yoloRISC today randomly and I found some stuff had broken | 21:19 |
| daveshah | I had to apply https://github.com/chipsalliance/rocket-chip/pull/2603 | 21:19 |
| daveshah | don't know if that will affect LiteX too, but if you get strange errors try that | 21:20 |
| somlo | good to know, thanks! | 21:21 |
| somlo | daveshah: hadn't thought about yoloRISC in a long time (that was before I discovered LiteX) | 21:22 |
| daveshah | yeah, I wanted to try it as a simple test with a testbench but it doesn't break | 21:22 |
| somlo | was wondering about that... | 21:23 |
| daveshah | even the simplest LiteX SoC (no DDR3/ethernet/sdcard, default rocket config, 20MHz clock) fails though | 21:24 |
| somlo | daveshah: that simplest LiteX SoC should also fit on a versa (45k ecp5). Wondering if it fails there as well... | 22:04 |
| somlo | not that I see why it shouldn't | 22:04 |
| daveshah | I think it probably would, given it fails on the Arty too using Yosys+Vivado | 22:05 |
| somlo | right, you did say that | 22:05 |
| somlo | interesting, upgrading rocket to #58a0e1052 works fine on the nexys4ddr (64-bit wide variant), but fails dram initialization on trellisboard (256-bit wide variant). "old" yosys (the one I used to successfully build working trellisboard bitstream using the old rocketchip) | 23:24 |
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