Saturday, 2020-11-21

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a314I'm running into a "assert c.size <= busword" (~line 500 of csr.py) failing when trying to import litespi into a design02:12
a314the CSR bus is 8 bits data, 14 bits address, but i tried raising it and that didn't seem to help02:12
zypyou tried raising what?07:36
zyplooks like the rxtx CSR defaults to 32 bits wide, which is not gonna fit on an 8 bit wide bus07:40
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iTitouHello everyone ! I'm new to LiteX (and fpga development in general). I'm trying to make a simple design with CSRs (https://github.com/titouanc/fpga-scratchpad/blob/master/03-CSR.py) but I don't see my CSRs in the generated CSV (http://paste.awesom.eu/51uz)13:08
tpbTitle: Paste it ยง (at paste.awesom.eu)13:08
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