Wednesday, 2020-11-11

« Tuesday, 2020-11-10 Index Thursday, 2020-11-12 »
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BkHi everybody! I have to connect my IP with axi-lite bus. I have generate a risc-v with cpu pico32 and bus axi-lite in my zybo board, but when I create a project in vivado i don't understand how to connect risc-v with my Ip. Can everyone help me?08:11
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BkHi everybody! I have to connect my IP with axi-lite bus. I have generate a risc-v with cpu pico32 and bus axi-lite in my zybo board, but when I create a project in vivado i don't understand how to connect risc-v with my Ip. Can everyone help me?09:25
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leonsIs there any specific reason why the CSR data width is defaulting to 8-bits? Intuitively this makes SW run slightly slower and I don't see any HW benefits (yet).13:57
zypwasn't the default recently changed from 8 to 32?14:10
leonszyp: Oh, I see the commit. I was using an older release, hence my default was still 8.14:45
leonsAnd the commit message explains that there is no negative impact, great!14:45
Bkanyone can help me?14:46
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mithro@leons Wider buses are harder to route on an FPGA17:31
mithro@leons as the CSR bus goes all over the FPGA (to pretty much every peripheral), it can be a driver of congestion17:33
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