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| promach3 | Is it technically feasible to use litescope to check litedram signals using usb on orangecrab ? | 05:22 |
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| st-gourichon-fid | Hi! We wish, from a microcontroller running C code, to access a wishbone bus through a SPI bridge connecting our microcontroller to the bus. | 10:40 |
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| st-gourichon-fid | We find https://docs.rs/wishbone-bridge/1.1.0/wishbone_bridge/ about a Rust implementation. We couldn't find plain documentation or a C implementation. Is there one somewhere? What do you recommend? | 10:41 |
| tpb | Title: wishbone_bridge - Rust (at docs.rs) | 10:41 |
| zyp | the rust implementation talks to this: https://github.com/xobs/spibone | 10:42 |
| zyp | protocol is documented there | 10:42 |
| st-gourichon-fid | Thanks zyp, looking. | 10:43 |
| st-gourichon-fid | Ah, this is really simple. Thanks! | 10:44 |
| st-gourichon-fid | zyp, is the protocole the same on UART as on SPI? "01 | AA | AA | AA | AA" etc? | 10:54 |
| zyp | no | 10:58 |
| st-gourichon-fid | mmh. Thanks, any doc? | 10:59 |
| st-gourichon-fid | It looks like including SPI-bridge-to-wishbone on our design costs much more gates than a UART-bridge-to-wishbone. | 11:00 |
| zyp | not sure, I went digging in the source some months ago: https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/uart.py#L380 | 11:00 |
| st-gourichon-fid | Mkay, trying to figure out from the hardware description... https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/uart.py#L257 class Stream2Wishbone. | 11:03 |
| st-gourichon-fid | Thanks. :-) | 11:03 |
| st-gourichon-fid | zyp, thanks, we think we figured out the UART wishbone bridge protocol from this description. | 11:16 |
| st-gourichon-fid | Mini UART-wishbone doc: Client sends [one byte to state "command" 01 02 03 or 04], then one byte "length", then 4 bytes "address", then the data, oh there's something strange in the hardware description. | 11:31 |
| st-gourichon-fid | Hmm, ah I got it. bytes_count is automatically stored on exactly the number of bits necessary so that it gets reset to zero "automatically". Nifty! https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/uart.py#L270 | 11:37 |
| st-gourichon-fid | Hmm, looks like there is a missed opportunity of saving a few gates here. Had CMD_*BURST* been implemented with codes 0 1 2 3, extracting simple bits would have been enough to decode READ=bit0 INCR=bit1. With values 1 2 3 4 code says "If((cmd == CMD_WRITE_BURST_INCR) | (cmd == CMD_WRITE_BURST_FIXED)," etc etc which looks like it consumes more gates. Can someone confirm? | 11:47 |
| st-gourichon-fid | But it's a breaking change of protocol. | 12:16 |
| st-gourichon-fid | I mean, changing 1 2 3 4 to 0 1 2 3 would be a breaking change. | 12:16 |
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