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| _florent_ | KSmith, Melkhior: the Kernel panic was due to a csr_data_width mismatch between the gateware and linux drivers (default csr_data_width changed recently to 32-bit), this is solved with https://github.com/litex-hub/linux-on-litex-vexriscv/commit/7b0c212b8051eb7416bbbd3c8826cf6625a4f80a | 13:13 |
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| _florent_ | Krickit: i just tried building ./versa_ecp5 --cpu-type=picorv32 on my machine and it builds correctly but Yosys/Nextpnr is a but outdated, i'll do another test with a recent version. | 13:17 |
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| Melkhior | _florent_ Indeed with the 'working' commit from buildroot (88a268354d) and HEAD you just committed, it works fine :-) | 14:30 |
| Melkhior | Thanks :-) | 14:32 |
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| powergraphic[m] | Are there any examples using litesata as part of a soc? I would like to access a data drive through Linux. | 16:35 |
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| kbeckmann | is it ok to ask netv2 questions here? can't seem to find a dedicated channel for it. anyway, i am wondering if there is a LiteX project setup where PCIe is enabled for netv2? | 18:53 |
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| st-gourichon-fid | zyp, regarding unaligned read, I'm just writing C code. Booting then reading 32-bit word at 0x80070001 works and provides expected value. Looks like it is supported, then. But: booting then reading 32-bit word at 0x80070000 (works) then 32-bit word at 0x80070001 crashes. | 20:27 |
| st-gourichon-fid | 0x8007xxxx is flash. | 20:29 |
| st-gourichon-fid | Reading only 8-bit bytes from addresses and assembling them with a C macro works always. | 20:30 |
| st-gourichon-fid | #define READ32_LE(p) ( (((p)[3]) << 24 ) | (((p)[2]) << 16 ) | (((p)[1]) << 8 ) | (((p)[0]) ) ) | 20:30 |
| st-gourichon-fid | READ32_LE(0x80070000) followed by READ32_LE(0x80070001) works. | 20:31 |
| st-gourichon-fid | printf("%p", *((uint32_t *)0x80070000) ) printf("%p", *((uint32_t *)0x80070001) ) prints only one value | 20:33 |
| st-gourichon-fid | Smells like a bug in flash-handling logic? Anyone experienced this kind of behavior? zyp, _florent_ ? | 20:34 |
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| kbeckmann | another pcie question.. has someone managed to instantiate two or more PCIe PHYs on Artix-7 with LiteX? i'm giving it a go but it seems i get stuck on using multiple refclk/IBUFDS_GTE2, which I guess isn't physically supported (need to check the datasheet here). i'm asking here in case someone has already attempted this and can nudge me in the right direction. I guess sharing one refclk between the | 23:50 |
| kbeckmann | links is preferrable. | 23:50 |
| kbeckmann | for context i want to build something that intercepts a PCIe link, forwarding TLPs between one uplink and one downlink. so sharing one refclk for both tx ports shouldn't be a problem if i understand things correctly. | 23:52 |
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