Monday, 2020-10-19

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futarisIRCclouddkozel: https://twitter.com/assortedhackery/status/131784955462929612902:37
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krickithi everybody12:59
daveshahhi!12:59
krickithi everybodhi daveshah12:59
krickiti have a problem with liteX13:00
krickiti used a folder gateware in my fpga tool13:00
krickitbut when i try to syntetize there are a lot of errors13:01
daveshahWhat errors?13:01
krickiti think that there isn't a pico's module13:01
daveshahYes, you will need to add that file too13:01
daveshahhave a look at the tcl/ys/whatever file litex generates in the gateware folder for the path for that13:02
krickitok, thanks i try13:02
krickitif i have problems can i ask you?13:02
st-gourichon-fidHi everyone. Class DFUProg does not provide any hint when things go wrong: https://github.com/enjoy-digital/litex/blob/master/litex/build/dfu.py#L1413:17
st-gourichon-fidCould be return code or exception. Dunno what is the stance here regarding pythonicity of code.  Anyway I coded near-trivial changes to propagate return code from cp/dfu-suffix/dfu-util to caller, which allows caller scripts to at least exit with a non-zero return code when things went wrong.13:18
st-gourichon-fidTL;DR:  Before change, failure goes unnoticed in build (including CI build etc), after change failure gets noticed.   Can do quick PR.13:19
krickitRunning DRC...14:10
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KrickitRunning DRC...15:03
Krickitprobably i didn't understand steps:15:16
Krickiti follow guide here https://github.com/enjoy-digital/litex15:17
Krickiti open targets folder and i run the python for my board15:18
Krickitnow I have the gateware folder and i add picorv file inside15:18
KrickitI create a project in my fpga tool with all files and i run synthesis15:19
Krickit?15:20
keesjwhat is the question?16:09
keesjst-gourichon-fid: nice20:12
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