Wednesday, 2020-10-07

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acathlaWhy do we have 8 bits CSR on a 32 bits VexRiscv ? #define CONFIG_CSR_DATA_WIDTH 813:31
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_florent_acathla: it's still the default, but this could be changed now that the different cores have been validated with it.14:31
_florent_i'm going to change it14:32
acathlaOk, nice.14:34
_florent_done :): https://github.com/enjoy-digital/litex/commit/898743c344d53568b98e4e4c225067659711303c14:38
tpbTitle: soc: change default CSR bus data-width to 32. · enjoy-digital/litex@898743c · GitHub (at github.com)14:38
acathlaPerfect! Merci =)14:46
acathlaoh, you pushed the changes to the fomu target. Do you know why SPI works in 1x while it should be in 4x like in foboot?14:52
acathlamay be xobs knows why...14:53
xobsNo idea. Maybe something got changed upstream with Hacker vs PVT revisions?14:54
acathla_florent_ based it on icebreaker, may be icebreaker just has 1x SPI that's all14:59
acathlaHum, no, SpiFlash(platform.request("spiflash4x"), dummy=6, endianness="little")15:00
_florent_acathla: i've not yet been able to get it working in 4x mode (but i haven't spent a lot of time on this), but i'm planning to look a this for both iCEBreaker and Fomu15:00
_florent_acathla: it's possible i was just using a wrong dummy cycle15:01
acathlaI don't know how to choose the right dummy cycle... I tried one config but failed too.15:08
_florent_On Fomu/PVT it should be 6, but i suspect there is something else15:21
scientesIf you have Fomu building I would love to hear how15:35
acathlascientes, new version, you just need to get and modify a bit a file of valentyusb15:41
acathlaIs it normal I cannot read back a CSRStorage ?16:02
acathlamay be it's CSRAccess.ReadOnly by default...16:05
acathlaCSRField("tx_power", offset= 8, size=2, reset=1, access=CSRAccess.WriteOnly, description="Transmition power, 0 is off, 3 is the maximum"),16:17
acathlaIt says : assert access is None or (access in CSRAccess.values())16:17
acathlahow do I fill the access= field?!16:17
acathla_florent_, did you try this?16:25
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