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| _florent_ | somlo: thanks for the Nexys4DDR test. I tested with several boards (7-Series, Ultrascale, ECP5, etc...) but the Nexys4DDR is indeed bit different (HalfRate PHY / DDR2), so possible i broke something for it, i'm going to look at that. | 07:13 |
|---|---|---|
| _florent_ | kbeckmann: great you got etherbone working on the colorlight. It's planned to look at the timing issues but the work has not yet started (but should in the next weeks), IIRC with Etherbone, most of the timings issues were directly in the Etherbone core/UDP/IP stack, the PHY should already use the DDR primitives: https://github.com/enjoy-digital/liteeth/blob/master/liteeth/phy/ecp5rgmii.py | 07:18 |
| tpb | Title: liteeth/ecp5rgmii.py at master · enjoy-digital/liteeth · GitHub (at github.com) | 07:18 |
| _florent_ | (but IDDRX1F and ODDRX1F: https://github.com/enjoy-digital/litex/blob/master/litex/build/lattice/common.py#L80 / https://github.com/enjoy-digital/litex/blob/master/litex/build/lattice/common.py#L96) | 07:19 |
| tpb | Title: litex/common.py at master · enjoy-digital/litex · GitHub (at github.com) | 07:19 |
| kbeckmann | _florent_: alright, that's great to hear. my idea was to use IDDRX2F / ODDRX2F to cut the frequency in half once more. that should give us a good timing budget. but that will limit which pins that can be utilized, but would probably be nice to have anyway in a dense ECP5 design. | 07:22 |
| daveshah | I think the hard part is not the primitive, but making the downstream pipeline accept 16 or 32 bits per clock | 07:23 |
| kbeckmann | i see | 07:23 |
| daveshah | There was some work on this for 10GbE support but I don't know if it is complete | 07:24 |
| kbeckmann | 10GbE support would be really neat, saw the PR (https://github.com/enjoy-digital/liteeth/pull/21). I've been thinking of making an ECP5 board with a 10GbE external phy and an SFP+ connector. | 07:30 |
| tpb | Title: Add hooks and features for 10/25G implementation by jersey99 · Pull Request #21 · enjoy-digital/liteeth · GitHub (at github.com) | 07:30 |
| kbeckmann | i have this quite stupid project idea where i want to do a hardware implementation of "pixelvloed", which is basically a framebuffer that is updated over UDP, and then send it out with DVID/HDMI to a big screen. turns out this is a bit harder than i imagined since the memory accesses will be very random and trash the cache among other problems. but could be a fun project to have as a guiding goal | 07:38 |
| kbeckmann | for me at least :). | 07:38 |
| kbeckmann | daveshah: do you thing such a project would be a bad fit for the ECP5 or do you think it could handle it? 10GbE over XGMII, 2 x DDR3 (thinking double buffering might be required here), HDMI 4k over SERDES | 07:42 |
| daveshah | I think it will be quite ambitious timing wise, but maybe doable | 07:43 |
| kbeckmann | sounds like a challenge then ;D | 07:43 |
| daveshah | The main problem with XGMII is the number of pins | 07:43 |
| kbeckmann | right, that is quite massive. | 07:43 |
| daveshah | and the PHY availability being a bit meh | 07:43 |
| zyp | XAUI might be a better bet | 07:43 |
| kbeckmann | yeah, using e.g. VSC8486 | 07:44 |
| zyp | not sure PHY availability would be much better though | 07:44 |
| kbeckmann | but then i burn all my serdes, so i will need a hdmi 4k capable phy i think | 07:44 |
| daveshah | Yeah VSC8486 is pretty much the only option | 07:44 |
| kbeckmann | ah i see. i have just recently looked into it. | 07:45 |
| daveshah | It's not cheap though | 07:45 |
| daveshah | https://www.mouser.co.uk/ProductDetail/Microchip-Microsemi/VSC8486YSN-04?qs=ZrZOYhVIkebqtfV3la3T7Q%3D%3D | 07:45 |
| kbeckmann | mmm... | 07:45 |
| daveshah | practically more than the ECP5 | 07:45 |
| kbeckmann | economy-wise it would make much more sense to use a different fpga. but i like the ecp5 :) | 07:45 |
| kbeckmann | right. the -04 variant has XGMII + XAUI, and -11 has only XAUI. | 07:47 |
| kbeckmann | the -11 variant isn't that expensive, but yeah it will use the precious serdes. | 07:47 |
| zyp | if the serdes is precious, it might make more sense to make use of both the input side and the output side of it :) | 07:52 |
| zyp | i.e. a parallel HDMI PHY might need fewer pins than XGMII since it's output only | 07:55 |
| kbeckmann | good point | 07:57 |
| daveshah | OTOH, HDMI input would be really cool too | 08:03 |
| daveshah | 4k HDMI -> 10GbE would be a very nice capture device | 08:03 |
| kbeckmann | could have 2 hdmi ports on that board, one in and one out | 08:04 |
| daveshah | yeah | 08:05 |
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| sajattack[m] | o/ | 08:43 |
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