| *** tpb has joined #litex | 00:00 | |
| *** jaseg has quit IRC | 02:43 | |
| *** jaseg has joined #litex | 02:45 | |
| *** Degi has quit IRC | 02:59 | |
| *** Degi has joined #litex | 03:01 | |
| *** SpaceCoaster has quit IRC | 05:25 | |
| *** SpaceCoaster has joined #litex | 05:25 | |
| *** m4ssi has joined #litex | 06:50 | |
| *** m4ssi has quit IRC | 09:37 | |
| *** m4ssi has joined #litex | 09:50 | |
| *** CarlFK has joined #litex | 10:08 | |
| lkcl | does anyone know of examples where litex peripherals have been done as verilog? | 13:59 |
|---|---|---|
| lkcl | e.g. some opencores stuff - uart, i2c, or other? | 13:59 |
| *** feldim2425_ has quit IRC | 14:13 | |
| *** m4ssi has quit IRC | 16:10 | |
| *** feldim2425 has joined #litex | 16:29 | |
| _florent_ | lkcl: you can look here for I2C, PWM, UART, etc.... https://github.com/enjoy-digital/litex/blob/master/litex/tools/litex_gen.py | 19:26 |
| tpb | Title: litex/litex_gen.py at master · enjoy-digital/litex · GitHub (at github.com) | 19:26 |
| _florent_ | ah, but not sure i understood your question correctly | 19:27 |
| _florent_ | if that's the other way (integrating verilog code), i can try to find code | 19:28 |
| _florent_ | you can find here an example of I2C core integrated with LiteX: https://github.com/betrusted-io/gateware/blob/master/gateware/i2c/core.py | 19:30 |
| tpb | Title: gateware/core.py at master · betrusted-io/gateware · GitHub (at github.com) | 19:30 |
| lkcl | i need to be able to pull in e.g. opencores 16550 uart written in verilog | 19:45 |
| lkcl | and present it as a peripheral that can be added to litex | 19:45 |
| lkcl | and richard herveille's opencores RGB/TTL | 19:45 |
| lkcl | and i *think*.... that bunnie huang code is exactly it. | 19:47 |
| lkcl | eyy it's even richard herveille's i2c opencores rtl :) | 19:48 |
| lkcl | _florent_, thank you. | 19:52 |
| lkcl | _florent_: for ASICs, all tristate signals must not be handled by litex, the "_i", "_o", "_oe" signals must be brought out (individually, explicitly) and wired up directly to IO pad cells. | 20:30 |
| lkcl | i have easily been able to do an SDRAMPHY replacement class that handles this: | 20:30 |
| lkcl | https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/litex/florent/ls180soc.py;h=9c7547f7078522cedccb5cc38f2beed6e58b7f6b;hb=HEAD#l121 | 20:30 |
| tpb | Title: git.libre-soc.org Git - soc.git/blob - src/soc/litex/florent/ls180soc.py (at git.libre-soc.org) | 20:30 |
| lkcl | sorry, line 168 | 20:31 |
| lkcl | https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/litex/florent/ls180soc.py;h=9c7547f7078522cedccb5cc38f2beed6e58b7f6b;hb=HEAD#l168 | 20:31 |
| tpb | Title: git.libre-soc.org Git - soc.git/blob - src/soc/litex/florent/ls180soc.py (at git.libre-soc.org) | 20:31 |
| lkcl | however, GPIOTristate had to be completely replaced because it does not take a "gpio_phy_cls" parameter | 20:32 |
| lkcl | SDCard likewise because that does not take a "sdcard_phy_cls" parameter i had to duplicate very large sections of the code | 20:32 |
| lkcl | and SDRPad | 20:33 |
| lkcl | spi is good (no Tristate) | 20:34 |
| lkcl | uart is good (except i had to duplicate the code in add_uart because, again, you can't pass in your own PHY class) | 20:35 |
| lkcl | PWM is good | 20:35 |
| *** haley has joined #litex | 20:48 | |
| *** haley has quit IRC | 20:50 | |
| *** lf has quit IRC | 23:21 | |
| *** lf has joined #litex | 23:22 | |
Generated by irclog2html.py 2.17.2 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!