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| futarisIRCcloud | https://resources.aldec.com/acton/media/23474/risc-v-design--verification-with-fpga-hardware-in-the-loop-eu | 01:57 |
|---|---|---|
| tpb | Title: RISC-V Design & Verification with FPGA Hardware In The Loop (EU) (at resources.aldec.com) | 01:57 |
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| _florent_ | Hi | 06:41 |
| _florent_ | dkozel: it's possible to use Chipscope on LiteX design, but you'll have to use the generated names in the verilog. On LiteX designs, it's generally easier to use LiteScope, but in some specific cases i'm also using Chipscope | 06:44 |
| _florent_ | somlo: nice for the litescard driver, are both reads and writes working? | 06:45 |
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| acathla | What's the best way to build my own C code against a litex design? It builds a bios in build/software folder but Makefiles are somewhere else in litex. | 09:44 |
| sajattack[m] | good example here https://github.com/icebreaker-fpga/icebreaker-litex-examples/tree/master/c-riscv-blink | 09:48 |
| tpb | Title: icebreaker-litex-examples/c-riscv-blink at master · icebreaker-fpga/icebreaker-litex-examples · GitHub (at github.com) | 09:48 |
| acathla | sajattack[m], so I just manually copy the files I need? Or make links. | 10:03 |
| sajattack[m] | I'm not really sure how the code was generated, ask esden | 10:10 |
| sajattack[m] | the makefile should work | 10:12 |
| lkcl | _florent_: you may be interested to know, the creation of an ASIC-compatible "platform" is working well | 10:59 |
| lkcl | https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/litex/florent/ls180soc.py;hb=HEAD#l29 | 10:59 |
| tpb | Title: git.libre-soc.org Git - soc.git/blob - src/soc/litex/florent/ls180soc.py (at git.libre-soc.org) | 10:59 |
| lkcl | https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/litex/florent/libresoc/ls180.py;hb=HEAD | 10:59 |
| tpb | Title: git.libre-soc.org Git - soc.git/blob - src/soc/litex/florent/libresoc/ls180.py (at git.libre-soc.org) | 10:59 |
| lkcl | the only major "pain" was (after taking ulx3s.py) to work out how to do "build", and i had to have a right-old dig into litex for a few hours and eventually worked it out | 11:00 |
| lkcl | override GenericPlatform and cut/paste the verilog build code from LatticePlatform, that did the trick | 11:01 |
| lkcl | ahh it is ok to add a 3rd bus (in this case a JTAG master) to periph_buses, right? | 11:15 |
| lkcl | self.periph_buses = [ibus, dbus] | 11:15 |
| lkcl | in this case | 11:15 |
| lkcl | self.periph_buses = [ibus, dbus, wishbone_bus] | 11:15 |
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| _florent_ | lkcl: nice, what you are trying to do is very similar to the core generators except that you have to create your own ASICPlatform | 11:37 |
| _florent_ | you can maybe find inspiration in: | 11:38 |
| _florent_ | https://github.com/enjoy-digital/litepcie/blob/master/litepcie/gen.py | 11:38 |
| tpb | Title: litepcie/gen.py at master · enjoy-digital/litepcie · GitHub (at github.com) | 11:38 |
| lkcl | ah appreciatd | 11:38 |
| _florent_ | https://github.com/enjoy-digital/litedram/blob/master/litedram/gen.py | 11:38 |
| tpb | Title: litedram/gen.py at master · enjoy-digital/litedram · GitHub (at github.com) | 11:38 |
| _florent_ | https://github.com/enjoy-digital/liteeth/blob/master/liteeth/gen.py | 11:38 |
| tpb | Title: liteeth/gen.py at master · enjoy-digital/liteeth · GitHub (at github.com) | 11:38 |
| _florent_ | otherwise, for self.periph_buses, all the buses of the list will be connected yes | 11:39 |
| lkcl | ahh goood | 11:39 |
| _florent_ | (and adapted in width and standard if necessary) | 11:40 |
| lkcl | i was expecting that to work, i did however wonder if it would try to do something unexpected if there weren't 2 entries in the list | 11:40 |
| lkcl | okaay. excellent | 11:40 |
| _florent_ | the SoC builder is logging these informations while building the SoC, so you can see which peripheral is added, if it's eventually adapted, etc... | 11:41 |
| lkcl | as i'm adding JTAG - *real* JTAG (thanks to staf Chips4Makers for creating a full TAP FSM) | 11:42 |
| lkcl | is there a way to connect those 4 pins to openocd in sim.py? | 11:42 |
| _florent_ | not yet no, but that could indeed be useful | 11:43 |
| lkcl | i'd like to actually connect openocd to the simulation and e.g. single-step it, upload to memory and so on | 11:43 |
| lkcl | the most logical / simplest route would be a network port | 11:43 |
| _florent_ | acathla: you can find a minimal firmware in https://github.com/litex-hub/fpga_101/tree/master/lab004 | 11:43 |
| tpb | Title: fpga_101/lab004 at master · litex-hub/fpga_101 · GitHub (at github.com) | 11:43 |
| lkcl | hmmm although openocd can run as a server... http://openocd.org/doc/html/Server-Configuration.html | 11:45 |
| tpb | Title: OpenOCD Users Guide: Server Configuration (at openocd.org) | 11:45 |
| lkcl | hmmm | 11:45 |
| lkcl | _florent_, if i have a suite of pins how do i get at the subpins | 12:13 |
| lkcl | platform.request("jtag").request("tms")? | 12:13 |
| lkcl | or platform.request("jtag.tms")? | 12:14 |
| _florent_ | jtagpads = platform.request("jtag") | 12:14 |
| _florent_ | then jtagpads.tms | 12:14 |
| lkcl | ahh excellent thank you | 12:14 |
| lkcl | self.comb += self.cpu.jtag_tdi.eq(jtagpads.tdi) | 12:15 |
| lkcl | self.comb += jtagpads.tdo.eq(self.cpu.jtag_tdo) | 12:15 |
| lkcl | that look reasonable? | 12:15 |
| lkcl | seems to be DoingTheRightThing(tm) in the resultant verilog (hurrah) | 12:17 |
| lkcl | how the hell am i going to test this?? :) | 12:19 |
| lkcl | like... ok maybe i could write a migen JTAG FSM | 12:20 |
| lkcl | however there must be a way to "chain" the JTAG internally to a Versa ECP5 JTAG port | 12:20 |
| daveshah | There is the JTAGG primitive that lets you access the fabric from the JTAG port using some custom instructions | 12:21 |
| daveshah | Its not documented but a few people have used it successfully in the past | 12:21 |
| lkcl | daveshah: ah! did they happen to put some code somewhere in a public repository, do you know? | 12:22 |
| daveshah | Yeah, just trying to find it | 12:22 |
| daveshah | https://github.com/emard/ulx3s-misc/blob/27338b0081b3b441f2fa77769350fa777bd3bcf9/examples/jtag_slave/hdl/top/top_jtagg_slave.v | 12:23 |
| tpb | Title: ulx3s-misc/top_jtagg_slave.v at 27338b0081b3b441f2fa77769350fa777bd3bcf9 · emard/ulx3s-misc · GitHub (at github.com) | 12:23 |
| lkcl | staaar, whew. i wonder if it's similar to Xilinx BSCANE2 or something? | 12:23 |
| lkcl | ah ha! | 12:23 |
| daveshah | https://github.com/Spritetm/hadbadge2019_fpgasoc/blob/4ae8277c45e17e316bb4d46ce625c1507506cd36/soc/top_fpga.v | 12:23 |
| tpb | Title: hadbadge2019_fpgasoc/top_fpga.v at 4ae8277c45e17e316bb4d46ce625c1507506cd36 · Spritetm/hadbadge2019_fpgasoc · GitHub (at github.com) | 12:23 |
| lkcl | okaay. so "not quite actual jtag" but "more like how Xilinx BSCANE2 works" | 12:26 |
| lkcl | still, thank you - it's something i could use to run on the ECP5. | 12:27 |
| lkcl | haha of course i could just shove a USB JTAG adapter onto 4 spare pins.... :) | 12:41 |
| daveshah | I've done that in the past tbh | 12:58 |
| somlo | _florent_: writes work too; but there's something weird going on, like some sort of intensive internal polling -- the "computer" becomes really slow and unresponsive once the litex_mmc driver successfully finds and intializes the card | 13:13 |
| somlo | but I'm still happy -- fixing something that already kinda works is better than a brick doing *nothing* :) | 13:14 |
| somlo | also, back when I used spi-mode sdcard, the kernel was polling for the presence of the card, and could tell when it was inserted/ejected -- that's not (yet) working with litesdcard, and might have something to do with the slowness | 13:16 |
| lkcl | _florent_: ah ha! https://github.com/lowRISC/opentitan/tree/master/hw/dv/dpi/jtagdpi | 13:44 |
| tpb | Title: opentitan/hw/dv/dpi/jtagdpi at master · lowRISC/opentitan · GitHub (at github.com) | 13:44 |
| lkcl | aw fer goodness sake | 13:52 |
| lkcl | https://github.com/enjoy-digital/litex/tree/master/litex/build/sim/core/modules/jtagremote | 13:52 |
| lkcl | lol | 13:52 |
| tpb | Title: litex/litex/build/sim/core/modules/jtagremote at master · enjoy-digital/litex · GitHub (at github.com) | 13:52 |
| lkcl | _florent_: that's exactly what i need :) | 13:52 |
| * lkcl facepalm | 13:52 | |
| lkcl | this will be hilarious if it works. | 14:02 |
| lkcl | how is "configurations" specified for litex modules? | 14:02 |
| lkcl | ext_module_s ext_mod | 14:02 |
| lkcl | there must be some sort of config file created which contains "serial2tcp" config data (the port number) | 14:04 |
| lkcl | and so on | 14:04 |
| lkcl | ahh JSON files :) | 14:05 |
| lkcl | SimConfig | 14:05 |
| lkcl | SimConfig.add_module() - "args" i assume. so can set port=9999 (or whatever is needed for openocd) | 14:07 |
| somlo | lkcl: just out of curiosity, are you doing a latex asic with the google skywater pdk thing, or is this something unrelated? | 14:10 |
| somlo | s/latex/litex/ :D | 14:10 |
| somlo | muscle memory is still a thing, apparently, after all these years :) | 14:10 |
| lkcl | somlo, :) i have workds where i do that | 14:11 |
| * lkcl just accidentally did it lol | 14:11 | |
| lkcl | alliance / coriolis2. | 14:12 |
| lkcl | with help and collaboration of Staf Verhaegen, from Chips4Makers | 14:12 |
| lkcl | he is handling the NDAs with https://europractice-ic.com/ | 14:12 |
| tpb | Title: EUROPRACTICE | IC Service (at europractice-ic.com) | 14:12 |
| somlo | lkcl: cool, thanks | 14:13 |
| somlo | chip fabrication is a thing I know nothing about, but feel an obligation to learn about | 14:13 |
| lkcl | yeah, very! with NLnet sponsorship paying for the MPW we can "experiment" and learn without having to pay EUR 18,000 | 14:14 |
| somlo | my uni has a 4-5 semester course sequence in the ECE dept (free to staff/employees who can convince the prof to let them enroll) | 14:14 |
| lkcl | somlo: yes. things are definitely stepping up a gear | 14:14 |
| lkcl | nice! | 14:14 |
| somlo | but then covid happened, and I don't feel like taking in-person classes for another while :) | 14:14 |
| lkcl | somlo: get plenty of morning sunlight, and when you can't, get some pharmaceutical-grade 50,000 AU Vitamin D | 14:15 |
| lkcl | and if you do get it for god's sake order and absolutely insist to the people that are looking after you to provide you with micro-aerosolised doses of the steroids used for treating asthma. | 14:16 |
| lkcl | getting there | 14:36 |
| lkcl | build/sim/core/sim.c Could not find interface jtag with index 0 | 14:37 |
| lkcl | now i have to call... platform.extensions... something? | 14:37 |
| lkcl | i've seen this somewhere in spi_sdcard | 14:37 |
| lkcl | dang! | 14:41 |
| lkcl | that worked. had to remember to actually request the jtag platform and connect up the pins just like for the LS180 ASIC | 14:42 |
| lkcl | holy s***! Info : JTAG tap: auto0.tap tap/device found: 0x000018ff (mfg: 0x47f (<invalid>), part: 0x0001, ver: 0x0) | 14:44 |
| lkcl | that's just stunning. | 14:45 |
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| st-gourichon-fid | Hi all, including _florent_ . We are concerned about building software without manually copying csr.h and the like. We are aware about linker.ld and cousins. | 16:43 |
| st-gourichon-fid | We now have a working design with SERV, can run lxterm. From your link https://github.com/litex-hub/fpga_101/blob/master/lab004/firmware/Makefile we can compile the software. | 16:43 |
| tpb | Title: fpga_101/Makefile at master · litex-hub/fpga_101 · GitHub (at github.com) | 16:43 |
| st-gourichon-fid | Generated files for a design include output_format.ld and regions.ld which is good. We are comparing the various existing linker.ld to figure out. | 16:44 |
| st-gourichon-fid | TL;DR: Is https://github.com/litex-hub/fpga_101/blob/master/lab004/firmware/linker.ld suitable to compile on "any" design based on your gist https://gist.github.com/enjoy-digital/82ed88b77ef0b1e3e91b0592e44eaa14 or are there caveat? | 16:45 |
| tpb | Title: fpga_101/linker.ld at master · litex-hub/fpga_101 · GitHub (at github.com) | 16:45 |
| st-gourichon-fid | Mmh, code does not compile because irq_setie not defined. Is it normal that https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/serv/irq.h is empty? | 16:57 |
| tpb | Title: litex/irq.h at master · enjoy-digital/litex · GitHub (at github.com) | 16:57 |
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| esden | acathla: sajattack[m] the code for the C example is generated by litex. These are the same headers as the ones used for the bios. I just copy them out from the litex build directory. I thought I described it in one of the README files... You will need to copy the headers out of litex every time you change anything regarding CSRs. | 19:30 |
| esden | rust example is much more clever, it uses the generated svd, and on the fly generates the necessary glue definitions for you. | 19:32 |
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| sajattack[m] | yeah I'm more familiar with how the rust side works | 20:28 |
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