| *** tpb has joined #litex | 00:00 | |
| *** jaseg has quit IRC | 02:06 | |
| *** jaseg has joined #litex | 02:09 | |
| *** Degi has quit IRC | 03:05 | |
| *** Degi has joined #litex | 03:07 | |
| *** awordnot has quit IRC | 04:43 | |
| *** civec has joined #litex | 04:43 | |
| *** awordnot has joined #litex | 04:44 | |
| *** kgugala has quit IRC | 06:32 | |
| *** kgugala has joined #litex | 06:33 | |
| *** kgugala_ has joined #litex | 06:33 | |
| *** kgugala has quit IRC | 06:37 | |
| *** kgugala_ has quit IRC | 06:49 | |
| *** kgugala has joined #litex | 06:49 | |
| *** jaseg has quit IRC | 08:04 | |
| *** jaseg has joined #litex | 08:53 | |
| acathla | Line https://github.com/enjoy-digital/litex/blob/a39660fa99b27b765e9115dcd3c77fde53db5906/litex/soc/integration/soc.py#L1105 tries to import cdc_eptri from valentyusb but I can only fin eptri.py | 10:33 |
|---|---|---|
| tpb | Title: litex/soc.py at a39660fa99b27b765e9115dcd3c77fde53db5906 · enjoy-digital/litex · GitHub (at github.com) | 10:33 |
| *** civec has quit IRC | 10:42 | |
| acathla | Ok, found it in a different branch | 12:14 |
| *** kgugala_ has joined #litex | 12:40 | |
| *** kgugala has quit IRC | 12:43 | |
| *** kgugala has joined #litex | 12:50 | |
| *** kgugala_ has quit IRC | 12:53 | |
| st-gourichon-fid | Hi. Thanks _florent_ for this: <_florent_> st-gourichon-fid: this is working: https://gist.github.com/enjoy-digital/82ed88b77ef0b1e3e91b0592e44eaa14 . It needed tweaking but this definitely helps. | 13:33 |
| tpb | Title: Fomu · GitHub (at gist.github.com) | 13:33 |
| st-gourichon-fid | For anyone interested, it provides an example design with SERV (Serial Risc-V). | 13:35 |
| *** kgugala_ has joined #litex | 14:36 | |
| *** kgugala has quit IRC | 14:38 | |
| *** kgugala has joined #litex | 14:49 | |
| *** kgugala_ has quit IRC | 14:53 | |
| tucanae47 | hello, has anyone recentyly try wishbone-tool with UARTWishboneBridge, im trying to get similar beheviour as fomu modifying CSR registers or just Memory, But without CPU, and be able to see memory from wishbone-tool. so far i can synthesize and upload program on fpga, but when trying `wishbone-tool -s terminal --csr-csv build/csr.csv` i really dont know how to proceed, here is my current code | 15:39 |
| tucanae47 | https://gist.github.com/tucanae47/8915148b9476066cc8194d29e5387194, i dont get a reply from the bridge | 15:39 |
| *** somlo has quit IRC | 16:04 | |
| *** somlo has joined #litex | 16:05 | |
| zyp | tucanae47, if you don't have a cpu, -s terminal is probably not gonna do anything useful :) | 16:11 |
| *** CarlFK has quit IRC | 16:16 | |
| tucanae47 | thanks! ops. thats rigth i missed that gonna try like that, but then csr should still make sense isnt it? (im sort of new to this) if i do like `./wishbone-tool --serial /dev/ttyUSB1 --csr-csv build/csr.csv 0x4000000` still the same | 16:19 |
| zyp | I don't think wishbone-tool on its own is gonna let you peek/poke memory, at least the version I've got here doesn't | 16:37 |
| zyp | but with -s wishbone it'll act as a bridge for litex-client | 16:38 |
| *** CarlFK has joined #litex | 16:43 | |
| acathla | tucanae47, wishbone-tool should read the bus at 0x4000000, be sure the serial port is not used by something else, like modemmanager on ubuntu | 16:51 |
| *** CarlFK has quit IRC | 19:57 | |
| *** CarlFK has joined #litex | 20:11 | |
| *** st-gourichon-fid has quit IRC | 21:09 | |
| awordnot | anybody ever hit memory init failures with VexRiscv SMP? I'm getting this on a nexys4ddr: https://upaste.anastas.io/2EsjYy | 21:11 |
| awordnot | the non-SMP variant works fine | 21:11 |
| *** st-gourichon-fid has joined #litex | 21:49 | |
| somlo | litex+rocket+linux can now mount a proper (*not* SPI-mode) liteSDcard: https://imgur.com/a/JfRYli0 | 22:41 |
| tpb | Title: Imgur: The magic of the Internet (at imgur.com) | 22:41 |
| somlo | antmicro litesdcard driver with a bunch of cleanup hacks (which I'm still in the process of cleaning up further before pushing to https://github.com/litex-hub/linux/tree/litex-rocket-rebase) | 22:43 |
| tpb | Title: GitHub - litex-hub/linux at litex-rocket-rebase (at github.com) | 22:43 |
| *** lf_ has joined #litex | 23:25 | |
| *** lf has quit IRC | 23:25 | |
| *** FFY00 has quit IRC | 23:42 | |
| *** FFY00 has joined #litex | 23:43 | |
| *** FFY00 has quit IRC | 23:47 | |
| *** FFY00 has joined #litex | 23:48 | |
| *** FFY00 has quit IRC | 23:49 | |
| *** FFY00 has joined #litex | 23:50 | |
Generated by irclog2html.py 2.17.2 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!