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| lkcl | futarisIRCcloud: hoo boy, 900k LUTs and 8GB of RAM, dang! | 10:28 |
|---|---|---|
| daveshah | These are pretty cool too | 10:30 |
| daveshah | https://www.ebay.com/itm/SQRL-BCU-1525-VCU-1525-FPGA/303567124491 | 10:30 |
| tpb | Title: SQRL BCU-1525 / VCU-1525 FPGA | eBay (at www.ebay.com) | 10:30 |
| daveshah | 2.5M logic cells, 4 DDR4 DIMMs, 2xQSFP28 | 10:30 |
| daveshah | not HBM like the fk33 tho | 10:30 |
| lkcl | there's a bug in SDRIO | 10:45 |
| lkcl | - return InferedSDRIO(dr.i, dr.o, dr.clk, dr.clk_domain) | 10:45 |
| lkcl | + return InferedSDRIO(dr.i, dr.o, dr.clk) # dr.clk_domain) | 10:45 |
| lkcl | litex/build/io.py | 10:45 |
| lkcl | anyone know the "correct" fix here? | 10:46 |
| miek | https://github.com/enjoy-digital/litex/commit/9950e75654683affbe04c0e9a670013c0dc7543b | 10:55 |
| tpb | Title: build/io: fix InferedSDRIO (thanks @mtdudek). · enjoy-digital/litex@9950e75 · GitHub (at github.com) | 10:55 |
| dkozel | futarisIRCcloud: Thanks! With GRCon done now I'm definitely getting back to gr-litex | 11:59 |
| dkozel | Several folks have bought CEL215 boards now so it'll be good to have a group working on it | 11:59 |
| futarisIRCcloud | I have two CLE-215+ here. And a HackRF. | 13:04 |
| dkozel | futarisIRCcloud: nice! I'm at the point where i need to figure out how to setup DMA from the litePCIe interface to a core on the bus and then back to PCIe | 13:06 |
| dkozel | I have the GNU Radio side working where I can stream to/from the PCIe in loopback | 13:07 |
| dkozel | It's been sitting undocumented for a while. Need to get it posted | 13:10 |
| dkozel | probably there's some catching up with LiteX and litePCIe to do | 13:10 |
| lkcl | PID USER PR NI VIRT RES SHR S %CPU %MEM TIME+ COMMAND | 13:44 |
| lkcl | 365243 lkcl 20 0 11.073g 0.010t 14216 R 100.0 17.0 26:21.76 yosys | 13:44 |
| lkcl | yee-hee-yowwwser! | 13:44 |
| lkcl | that's compiling a litex-generated pinout for an ASIC | 13:45 |
| daveshah | The memories will be being bitblasted | 13:45 |
| lkcl | daveshah: ahh | 14:16 |
| lkcl | it may be interfering with yosys-abc (which is segfaulting) | 14:17 |
| daveshah | The solution will either to have LiteX use memory compiler primitives instead; or remove all calls to memory_map in your Yosys script so you are left with $mem cells (less ideal but maybe you can use memory_bram to map them to your ASIC primitives) | 14:18 |
| lkcl | daveshah: makes some sense, i know that staf (chips4makers) and jean-paul (coriolis2) will understand that | 14:20 |
| lkcl | daveshah: you mean stuff like this: | 14:40 |
| lkcl | Consolidated identical input bits for $mux cell $memory\mem$rdmux[0][9][93]$90622: | 14:40 |
| lkcl | etc. etc. ? | 14:40 |
| lkcl | if that happens, equals Bad(tm)? | 14:40 |
| daveshah | If the memory is large enough, yes | 14:41 |
| daveshah | That's some attempt to optimise the memory after it has been bitblasted by the looks of things | 14:42 |
| lkcl | it's a... 64k ROM | 14:42 |
| lkcl | 1 of them is a 64k ROM (litex BIOS) | 14:42 |
| lkcl | the other's the SRAM which i reduced to 8k | 14:43 |
| lkcl | i don't actually want a ROM in the ASIC, not for a test chip, that is. | 14:43 |
| lkcl | will be using JTAG to write to SRAM | 14:43 |
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| lkcl | libresoc 180nm "peripherals" created by litex, plus the core, compiled / routed under coriolis2. yay! | 23:46 |
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