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| futarisIRCcloud | dkozel: https://youtu.be/Acjly9UC_5Y - Great zoom call. | 11:14 |
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| leons | I'm currently working on porting an OS to a Litex SoC with a VexRiscv CPU. Is there any place where I can find (human readable / code) documentation, as you'd find for SoCs you can buy? I'm quickly getting used to reading/writing LiteX/nMigen code, however I don't find much info about VexRiscv at all | 17:46 |
| leons | For instance, does it have a RISC-V machine timer, if yes how do I control it, which CSRs do what, etc. | 17:47 |
| leons | https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/vexriscv/core.py#L64 | 17:57 |
| leons | In this specific case the VexRiscvTimer & interrupt wiring up to the CPU leads me to believe this is the mtimer implementation, so I guess VexRiscv does not have one builtin? | 17:57 |
| tpb | Title: litex/core.py at master · enjoy-digital/litex · GitHub (at github.com) | 17:57 |
| zyp | for the vexriscv core itself, you should probably look at the vexriscv project for documentation: https://github.com/SpinalHDL/VexRiscv | 19:13 |
| tpb | Title: GitHub - SpinalHDL/VexRiscv: A FPGA friendly 32 bit RISC-V CPU implementation (at github.com) | 19:13 |
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