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| futarisIRCcloud | https://twitter.com/pdp7/status/1298298945257570304 | 17:37 |
|---|---|---|
| pdp7 | yes, I have shared notes | 18:11 |
| pdp7 | unfortunately we didn't have everyone that I would have liked | 18:11 |
| pdp7 | did have several kernel maintainers that gave some suggestions | 18:12 |
| pdp7 | I would say the strongest opinion was that regmap is the way to go for CSR access | 18:12 |
| pdp7 | Kernel maintainers like Jonathan Cameron (IIO) felt that the performance hit of 2 indirect calls is not an issue | 18:13 |
| pdp7 | https://linuxplumbersconf.org/event/7/contributions/705/ | 18:13 |
| tpb | Title: Linux Plumbers Conference 2020 (24-28 August 2020): BoF: upstream drivers for open source FPGA SoC peripherals ยท Indico (at linuxplumbersconf.org) | 18:13 |
| pdp7 | I typed while people talked so didn't capture everything | 18:15 |
| pdp7 | https://linuxplumbersconf.org/event/7/contributions/705/attachments/608/1106/notes.html | 18:15 |
| tpb | Title: 5b92d0df (at linuxplumbersconf.org) | 18:15 |
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| conmega | I wish I had known about that presentation, I'd have loved to have seen it. Will have to keep a better eye out going forward :) | 19:04 |
| somlo | pdp7: any feel for whether the kernel folks would rather prefer 32-bit-only litex drivers, to be "64-bit-ified" later, or if width agnostic (32 *and* 64 bit support) should be added right from the start ? | 19:08 |
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| pdp7 | unfortunately, that aspect was not covered. but I can follow up as all the participants like Jonathan Cameron are still around the virtual conference. | 19:15 |
| pdp7 | conmega: it was really more of a discussion session to get some agreement on the right way to tackle problems. unfortunately, I didn't know it was accepted until about a week and half ago and thus wasn't able to get all the people that I think were necessary invovled | 19:16 |
| pdp7 | the upside is at least several more experienced linux kernel developers are interested in what is going on with the LiteX drivers and CSR's | 19:17 |
| conmega | That's fair, I am really glad you started the discussion though! Really really happy to see this this type of discussion around this since I was looking into what it would be like to write some kernel drivers for additions to liteX | 19:17 |
| pdp7 | I'll try to summarize and post toe linux-litex mailing list. I proposed this session in June when there was a lot of active discussion https://groups.google.com/d/msg/linux-litex/fJLlcsuBibY/3vP8_7nGAwAJ | 19:19 |
| tpb | Title: Google Groups (at groups.google.com) | 19:19 |
| pdp7 | but the lack of late registration and timezones kept some people from being able to particpation | 19:19 |
| conmega | Also I didn't realize microwatt was added to liteX, that's pretty neat. I work at IBM, on their Z mainframe hardware though, so not directly involved with P but its still awesome stuff. | 19:19 |
| conmega | Cool thanks for the link, I'll have to read through all that later. | 19:20 |
| pdp7 | conmega: yeah, i would recommend you contact Benjamin Herrenschmidt who would have attended if it wasn't at 12am in australia | 19:20 |
| pdp7 | https://groups.google.com/g/linux-litex/c/laH606Zd1rk/m/1y9dzZR0AwAJ | 19:21 |
| tpb | Title: Sign in - Google Accounts (at groups.google.com) | 19:21 |
| pdp7 | hmm | 19:21 |
| pdp7 | unfortunately linux-litex is a google group so sometimes links don't work right | 19:21 |
| pdp7 | their address is Benjamin Herrenschmidt <[email protected]> | 19:21 |
| conmega | Cool thanks! | 19:22 |
| conmega | I first need to look into some of the hardware development, I have been reading the PCIe base spec and scowering the litepcie and litex code-base to get a bit better of an understanding of how things are working. | 19:23 |
| pdp7 | neat! | 19:23 |
| conmega | I'd like to add a root port to it so we can start playing with having a root port off riscV for Linux, for less than the 3 grand it cost previously for the sifive dev kit, although now with the 500 dollar icicle its probably less enticing | 19:24 |
| conmega | but ultimately it will be interesting as a learning experience and seeing where I can get with it | 19:24 |
| conmega | Looks like honestly the hardest part is just architecting it properly (ie sanely) following a similar implementation as the Xilinx AXI bridge would lend to leaning on their kernel driver code which is pretty simple | 19:25 |
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| pdp7 | conmega: that is an interesting idea to have a PCIe root port. | 19:44 |
| conmega | seems like _florent_ was also interested in adding support for a root port as-well, I have an email I was writing up to send them but haven't gotten around to it. | 19:45 |
| conmega | I'd love to see it to give a wider access to people to do linux development for PCIe endpoint devices, it was really cool to see people get linux running on the sifive boards with a GUI and everything | 19:46 |
| conmega | but even simply playing with network controllers and stuff and verifying drivers and things work would be great | 19:46 |
| conmega | also having a root port for talking to things like NVMe storage and such could be useful for certain applications | 19:47 |
| conmega | it seems very popular to be hanging NVMe drives off FPGAs as of late, I believe even IBM has some open-source HDL for an NVMe drive attach to FPGA for special networking processing or something | 19:47 |
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| benh | I wish I could have attended ... but it was really not a good time for me, I've ended up skipping LPC completely | 23:17 |
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