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somlo | lkcl: good news, congrats! So, that's with standard litex-bios leveling code and everything, right ? | 00:26 |
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lkcl | yes - but only in simulation | 00:53 |
lkcl | which is both hilarious and odd | 00:53 |
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lkcl_ | that's... interesting. the memtest "data" answers (MEMTEST_DATA_DEBUG) are always offset/rotated by 16 bits | 10:58 |
lkcl_ | [data 0xf238]: 0x6a29d42e vs 0xd42e3517 | 10:58 |
lkcl_ | [data 0xf239]: 0x3517ea37 vs 0xea371a88 | 10:58 |
lkcl_ | [data 0xf23a]: 0x1a88751b vs 0x751b8d44 | 10:58 |
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lkcl_ | the hypothesis here is that some internal litex arbiter-counters (the ones that monitor N-to-M transfers) get out-of-sync | 12:35 |
daveshah | I have seen similar issues where the problem is the bitslip/latency config of the DDR3 interface | 12:44 |
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lkcl_ | ah? you mean that line "read_latency = 2 + cl_sys_latency + 2 + log2_int(4//nphases) + 5," | 17:31 |
lkcl_ | in ecp5ddrphy.py? | 17:32 |
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