Monday, 2020-08-17

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somlolkcl: good news, congrats! So, that's with standard litex-bios leveling code and everything, right ?00:26
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lkclyes - but only in simulation00:53
lkclwhich is both hilarious and odd00:53
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lkcl_that's... interesting.  the memtest "data" answers (MEMTEST_DATA_DEBUG) are always offset/rotated by 16 bits10:58
lkcl_[data 0xf238]: 0x6a29d42e vs 0xd42e351710:58
lkcl_[data 0xf239]: 0x3517ea37 vs 0xea371a8810:58
lkcl_[data 0xf23a]: 0x1a88751b vs 0x751b8d4410:58
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lkcl_the hypothesis here is that some internal litex arbiter-counters (the ones that monitor N-to-M transfers) get out-of-sync12:35
daveshahI have seen similar issues where the problem is the bitslip/latency config of the DDR3 interface12:44
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lkcl_ah?  you mean that line "read_latency  = 2 + cl_sys_latency + 2 + log2_int(4//nphases) + 5,"17:31
lkcl_in ecp5ddrphy.py?17:32
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