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| bubble_buster | how do I "request" connectors from https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/orangecrab.py ? | 03:41 |
|---|---|---|
| tpb | Title: litex-boards/orangecrab.py at master · litex-hub/litex-boards · GitHub (at github.com) | 03:41 |
| bubble_buster | I tried platform.request("GPIO:6"), request("GPIO", 6), those didn't work. seems connectors are treated differently than io so they can't be accessed with request()? | 03:42 |
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| bubble_buster | ah, seems I need to define a new group of signals (which can leverage the naming provided by the connectors array) and pass that to add_extension() | 04:19 |
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| futarisIRCcloud | https://www.blackmagicdesign.com/au/products/decklink/techspecs/W-DLK-29 | 18:52 |
| tpb | Title: DeckLink – Tech Specs | Blackmagic Design (at www.blackmagicdesign.com) | 18:52 |
| CarlFK | I have had my eye on that | 19:00 |
| zyp | spartan 6 though | 19:22 |
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| davidcorrigan714 | daveshah Happen to be around? Had a Lattice licensing question I figured you might have some insight on | 19:33 |
| daveshah | Yeah sure | 19:33 |
| davidcorrigan714 | So I'm trying to get the PLL on the crosslink-nx working with LiteX. One hard part is that the IP generator in Radiant calculates some analog values to tune the PLL for the given frequency set. Can't find any documentation on the parameters, but lo and behold they're all calculated with a Python script in the IP generator data installed with | 19:35 |
| davidcorrigan714 | Radiant. Not entirely sure how to legally leverage that to include the calculations in an OSS project. The file says | 19:35 |
| davidcorrigan714 | # Lattice SG Pte. Ltd. grants permission to use this code# pursuant to the terms of the Lattice Reference Design License Agreement. | 19:35 |
| davidcorrigan714 | Which I think is this: | 19:35 |
| davidcorrigan714 | https://www.latticesemi.com/en/FileExplorer?media=%7B22D53623-3E8D-451E-9F0E-41785522946E%7D&document_id=39071 | 19:35 |
| tpb | Title: File Explorer - Lattice Semiconductor (at www.latticesemi.com) | 19:35 |
| daveshah | ianal, etc, but the maths in such a file should be a fact and not copyrightable | 20:14 |
| daveshah | The code is, and it is not compatible with any OSS license due to this clause | 20:15 |
| daveshah | personal, non-exclusive, non-transferable right to use and modify the Reference Design selected for download in source code form for the sole purposes of creating and implementing design to program Lattice programmable logic devices | 20:15 |
| davidcorrigan714 | Sounds right. Just have to figure out a way to separate the two. Suppose I can write out all the math then reimplement it in code, it's just a lot of math to sift through. | 20:17 |
| CarlFK | or approach them with some offer about "change the license on this code so we can promote your hardware" | 21:15 |
| CarlFK | mithro: ^^ I suspect you have things to say about this | 21:16 |
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| davidcorrigan714 | In the case of the PLL it's a pretty critical chunk of code and I really don't know how you'd leverage it for anything other than building designs for their hardware. Even if they'd release some documentation on the math it'd be a bit easier than trying to decipher the python. | 23:12 |
| lkcl_away | daveshah: oleee! POWER9 cmp instruction fixed - Memtest works | 23:57 |
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