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| avg | sajattack[m] What are you doing about RAM? Will be external? | 00:45 |
|---|---|---|
| sajattack[m] | in my testing I just gave it a 1k sram | 00:51 |
| sajattack[m] | but you could do an external sdram or something for sure | 00:52 |
| sajattack[m] | I was able to compile vexriscv minimal into an asic outside of litex | 00:53 |
| * sajattack[m] uploaded an image: 2020-08-10-180151_570x540_scrot.png (138KB) < https://matrix.org/_matrix/media/r0/download/matrix.org/QytCMUkglTMsCqtASPDLnptI > | 01:02 | |
| sajattack[m] | I'm not sure if it's a problem with litex or my naive approach to modifying the build script | 01:05 |
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| futarisIRCcloud | conmega: Which JTAG adapter are you using for the Acorn CLE-215+ ? | 05:34 |
| zyp | futarisIRCcloud, you didn't ask me, but I'm just using a generic ft232h breakout | 05:56 |
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| disasm[m] | <sajattack[m] "in my testing I just gave it a 1"> How about https://github.com/VLSIDA/OpenRAM ? | 12:20 |
| tpb | Title: GitHub - VLSIDA/OpenRAM: An open-source static random access memory (SRAM) compiler. (at github.com) | 12:20 |
| disasm[m] | I'm not sure it's easily embeddable in current flows, but anyway | 12:21 |
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| sajattack[m] | It's not ready yet | 16:56 |
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| conmega | futarisIRCcloud: I am using a clone J-link at the moment. I only happen to have an FT232R breakout kicking around right now and it doesn't even have all the pins broken out. So I need to order some things. Wasn't really a complaint as more of an observasion on my end :) | 17:51 |
| conmega | Actually, just happened across an amontec jtagkey on eBay for a good price, so grabbed that. FT232H with level shifting from 5V down to 1.4V so that will be nice. | 18:02 |
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| lkcl | hi all, have been setting up libresoc to run under litex. sim works, am just setting up on a versa-ecp5 (LFE5UM) | 19:41 |
| lkcl | as this is a "first iteration ever" i am identifying areas that need improvement | 19:41 |
| lkcl | however i would like to "just get it to work for now" | 19:41 |
| lkcl | currently there's a 37ns routing loop which limits the top clock frequency that this can run at to around 27 mhz | 19:42 |
| lkcl | my question therefore is: how can i set the frequency of the design clock to run at say... 16 mhz? | 19:43 |
| lkcl | or 75/4=18.75 for example | 19:43 |
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| lkcl | is it as simple as adding "--sys-clk-freq=18.75e6" to the BaseSoC parameters? | 19:43 |
| daveshah | passing it on the command line should work, yeah | 19:45 |
| daveshah | I don't know if you need the '=' though, I always use a space | 19:45 |
| lkcl | daveshah: ok ta | 19:47 |
| lkcl | started building @ 16e6, i'll let it run | 19:47 |
| * lkcl waves to daveshah | 20:16 | |
| daveshah | hi! | 20:17 |
| lkcl | 8mhz clock rate initialisation of versa-ecp5 dram: not quite working, there. | 20:17 |
| lkcl | also, whilst that's an 8mhz clock rate, it's actually a FSM at the moment | 20:18 |
| daveshah | You could see if it works with picorv32 at that rate | 20:18 |
| lkcl | so the actual instruction rate is... 1/8th of that | 20:18 |
| lkcl | ah good idea | 20:18 |
| lkcl | i'd have to bring it down to around 2mhz to be "on par" | 20:18 |
| daveshah | My guess is it is the DRAM interface clock, not the CPU IPS, that is the problem | 20:18 |
| daveshah | Unfortunately, that is fixed at 2x the system clock and not easily changeable | 20:19 |
| lkcl | ahh ok | 20:19 |
| lkcl | oh yes, i noticed that | 20:19 |
| lkcl | well... i could put a "fake" PLL (digital counter/divider) in | 20:19 |
| daveshah | It might be possible to use a faster processor to do DRAM init | 20:19 |
| daveshah | And then provide another AXI port or whatever that you CDC to your slow CPU under test | 20:20 |
| lkcl | i'm leaning towards a manual clock-counter (in nmigen). leave the main clock at 75mhz and fire the cpu clock using a DomainRenamer() | 20:21 |
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| lkcl | picorv32 memtest @ 16mhz... | 20:22 |
| lkcl | - bus errors: 98/256 | 20:22 |
| lkcl | - addr errors: 7717/8192 | 20:22 |
| lkcl | - data errors: 520871/524288 | 20:22 |
| * lkcl trying 20mhz | 20:22 | |
| lkcl | trying with picorv32 is a good idea, it's quite quick to build (a lot faster than libresoc, which is approaching the max LUTs of 45k) | 20:23 |
| avg | sajattack[m] Did you see the Skywater slack? http://join.skywater.tools/ | 20:24 |
| tpb | Title: Request invite to the skywater-pdk Slack! (at join.skywater.tools) | 20:24 |
| lkcl | SDRAM: 131072KiB 16-bit @ 80MHz | 20:24 |
| lkcl | Memtest at 0x40000000... | 20:24 |
| lkcl | [########################################] | 20:24 |
| lkcl | [########################################] | 20:24 |
| lkcl | - bus errors: 74/256 | 20:24 |
| lkcl | - addr errors: 7639/8192 | 20:24 |
| lkcl | - data errors: 475365/524288 | 20:24 |
| sajattack[m] | avg: yup I've been asking questions and chatting there | 20:26 |
| lkcl | 120 mhz DRAM: also fail :) | 20:27 |
| daveshah | Huh, maybe something has broken | 20:30 |
| daveshah | Does the default 75MHz system clock work? | 20:30 |
| lkcl | daveshah: yes, 75mhz is fine | 20:31 |
| lkcl | tried 40mhz clock (160mhz SDRAM), fail too | 20:31 |
| lkcl | 48mhz (192mhz SDRAM) _also_ fail. urk | 20:33 |
| lkcl | the average DDR3 IC _should_ work fine at around 200 mhz.... | 20:34 |
| daveshah | The DDR3 clock is only 100MHz | 20:35 |
| daveshah | litex is incorrectly reporting the transfer rate not the frequency | 20:36 |
| lkcl | ah | 20:36 |
| lkcl | SDRAM: 131072KiB 16-bit @ 300MHz | 20:36 |
| daveshah | litex disables DLL so low frequencies should be fine | 20:36 |
| lkcl | CPU: PicoRV32 @ 75MHz | 20:36 |
| daveshah | The problem is probably the various latency magic numbers in the PHY aren't right at such a low frequency | 20:36 |
| daveshah | Or, the problem is in the ECP5 IO logic | 20:37 |
| lkcl | well, i'm going to cheat and do a manual clock which halves the frequency | 20:38 |
| lkcl | nuts. | 20:38 |
| lkcl | i need to 1/4 the frequency, don't i? :) | 20:38 |
| lkcl | so that's a counter up to 8 (3 bits), test the top bit == true, that's the "clock" to send over the DomainRenamer() new clock domain | 20:39 |
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| lkcl | ah doh i need something a bit more sophisticated than a part-hack | 21:04 |
| lkcl | i need to do a level of indirection, add *another* DomainRenamer, sigh. | 21:11 |
| lkcl | daveshah: is there any other PLL that i could use to run things from, on the versa_ecp5, do you know? | 21:12 |
| daveshah | Yes there are three PLLs and LiteX should only use one of them | 21:15 |
| zyp | three? | 21:15 |
| lkcl | okaay. so hypothetically i could indeed do a separate sys clock running from that | 21:17 |
| lkcl | call it "core clock" or something | 21:17 |
| lkcl | however.... mm.... interacting with the wishbone bus is going to get interesting | 21:18 |
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