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| scientes | is migen also reasonable for ASIC designs? | 21:23 |
|---|---|---|
| sajattack[m] | migen can output verilog so yes | 22:38 |
| sajattack[m] | I was experimenting with a litex example project and openlane but I got an error I didn't understand | 22:39 |
| sajattack[m] | but there's no theoretical reason it shouldn't work | 22:40 |
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