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| futarisIRCcloud | Has anyone here JTAGed their Acorn CLE-215+ using something other than a FT2232 interface? My boards arrived earlier this week, and I've got breakout cables too. | 12:23 |
|---|---|---|
| futarisIRCcloud | DMA bus stuff looks promising. | 12:26 |
| zyp | why other than FT2232? | 12:30 |
| zyp | strictly speaking, I've been using a FT232, which is like half a FT2232 :p | 12:31 |
| zyp | but I figure whatever you've got available should work, no? | 12:31 |
| trabucayre | zyp: jtag with ft2232 is bitbang mode -> slow. But it work | 12:33 |
| zyp | no, it's using MPSSE and can run up to 30 MHz | 12:37 |
| trabucayre | FT232H yes, FT232E no | 12:40 |
| trabucayre | s/FT232E/FT232R/g | 12:41 |
| zyp | by FT2232 I assumed FT2232H | 12:43 |
| zyp | and yes, I've got a FT232H | 12:43 |
| futarisIRCcloud | https://github.com/osresearch/risc8 | 12:44 |
| tpb | Title: GitHub - osresearch/risc8: Mostly AVR compatible FPGA soft-core (at github.com) | 12:44 |
| trabucayre | for a tool I've played with ft2232, ft232h (digilent_hs2), ft232R and ft231x (ulx3s) so maybe I'm a bit too much picky with name :) | 12:48 |
| zyp | fair enough | 12:49 |
| zyp | are there any FT2232 variants without MPSSE? | 12:50 |
| trabucayre | I think no | 12:52 |
| trabucayre | Both C, D, L, H have MPSSE | 12:53 |
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| npcomp | futarisIRCcloud: I have some of the picoez cables, I was going to try to adapt them this weekend. | 16:32 |
| npcomp | q: do I need to worry about voltage mismatch for the CLE-215? | 16:32 |
| npcomp | Maybe I can't read the manual, but I don't see anywhere where it specifies if the jtag is 3.3v capable or what. | 16:33 |
| npcomp | I picked up a few different options for programming on ebay, hoping to finally solve the time/courage challenge this weekend. | 16:34 |
| zyp | npcomp, jtag and the 6-pin IO is 3.3V | 17:34 |
| zyp | the larger IO that's hidden under the heatsink edge is mixed 2.5/3.3V | 17:35 |
| zyp | https://bin.jvnv.net/file/ckrqE.jpg | 17:36 |
| zyp | that's how I did it :) | 17:37 |
| SpaceCoaster | Does that acorn FPGA work with the webpack version of Vivado? | 18:08 |
| daveshah | It's a 200T right? | 18:08 |
| daveshah | should be fine | 18:08 |
| SpaceCoaster | Nice, thanks. I just submitted a PR for LiteSPI on Lattice ECP5. I noticed in the readme for LiteSPI that it can generate Verilog to use it outside Litex. How? | 18:13 |
| SpaceCoaster | Can I just generate Verilog for any submodule? | 18:14 |
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| _florent_ | SpaceCoaster: not sure the generator has been done for LiteSPI, but you can look at https://github.com/enjoy-digital/litex/blob/master/litex/tools/litex_gen.py for a simple example of generator | 19:41 |
| tpb | Title: litex/litex_gen.py at master · enjoy-digital/litex · GitHub (at github.com) | 19:41 |
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| SpaceCoaster | _florent_: thanks, I was just curious. | 20:57 |
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| futarisIRCcloud | https://www.servethehome.com/molex-bittware-250-m2d-adds-xilinx-fpga-m-2-ocp/ | 23:46 |
| tpb | Title: Molex BittWare 250-M2D Adds Xilinx FPGAs to M.2 | ServeTheHome (at www.servethehome.com) | 23:46 |
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