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| _florent_ | somlo: Hi, the issue you had with Nexys4DDR/SDCard was probably https://github.com/enjoy-digital/litesdcard/commit/35d7d89606dced0e8522b9366f636d7477685680 | 16:53 |
|---|---|---|
| tpb | Title: phy/SDPHYIOGen: fix typo. · enjoy-digital/litesdcard@35d7d89 · GitHub (at github.com) | 16:53 |
| _florent_ | it's now working fine with Linux-on-LiteX-VexRiscv and should also work with Rocket | 16:54 |
| _florent_ | i still have to figure out something on the Trellisboard before you could use it, strangely the SDCard boot seems reliable when the probes of the logic analyzer are connected, but no longer works when probes are disconnected | 16:56 |
| _florent_ | somlo: also, it's now possible to add a dma_bus to the CPU, so you could add it to Rocket, if present, LiteX will use it for the DMAs: https://github.com/enjoy-digital/litex/commit/d38048baac06d41f9f887667d08453f5a0b82d93 | 17:00 |
| tpb | Title: soc: add initial DMA bus support (optionally provided by CPU(s) for c… · enjoy-digital/litex@d38048b · GitHub (at github.com) | 17:00 |
| _florent_ | somlo: we've been able to get test it successfully with VexRiscv SMP and LiteSDCard reading Linux images through the DMA port of the VexRiscv SMP cluster | 17:01 |
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| somlo | _florent_: I'm building it now (with the hacked rocket that shares mem+mmio over wishbone) | 17:35 |
| somlo | will report back once I see what it does | 17:36 |
| _florent_ | somlo: ok thanks | 17:36 |
| somlo | _florent_: tested with rocket on nexys4ddr; hangs at "booting from boot.json..." after pushing the bitstream with openocd; hitting reset gets it working OK about 50% of the time (the rest of the time after reset it hangs at "booting from boot.json" again | 18:00 |
| somlo | but when it works, it works perfectly :) | 18:00 |
| somlo | I'm guessing something about initialization/reset of the litesdcard gateware, maybe? | 18:01 |
| _florent_ | ok strange, can you provide me the bitstream? | 18:01 |
| somlo | _florent_: sent it to you via email | 18:03 |
| somlo | _florent_: same behavior if I s/rocket/vexriscv/ when building the bitstream | 18:10 |
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| qubic | hello, I might asking a dummy question so please forgive me about it :PIs it possible to simulate my own LiteX SoC with lxsim? | 22:05 |
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