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| _florent_ | lf_: i just wrote a wiki page about the Migen/nMigen situation: https://github.com/enjoy-digital/litex/wiki/Migen-nMigen | 09:40 |
|---|---|---|
| tpb | Title: Migen nMigen · enjoy-digital/litex Wiki · GitHub (at github.com) | 09:40 |
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| lf | _florent_: ah thx i will take a look at the minerva integration | 18:36 |
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| zyp | the way I see it, while integrating a nmigen core by treating it as a black box is easy, it has some disadvantages like not being able to easily hook up litescope to internal signals | 21:39 |
| zyp | that's what's been keeping me on migen so far | 21:40 |
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| loxodes | I'm running into problems writing a burst of words to SRAM over wishbone in a Migen module in a LiteX SoC, and I'm looking for ideas what the cause might be or on how to approach debugging. | 21:59 |
| loxodes | I've copied the wishbone writing approach from litex/soc/cores/uart.py (My wishbone writing code is here: https://github.com/loxodes/vna/blob/devel/breakouts/adc_32xx/software/ddr_test.py#L203) | 21:59 |
| tpb | Title: vna/ddr_test.py at devel · loxodes/vna · GitHub (at github.com) | 21:59 |
| loxodes | Currently I'm writing the same incrementing number to SRAM, i.e I write "1" 1024 times and then the next time I trigger a burst I'll write "2" 1024 times. | 21:59 |
| loxodes | The first 16 words writes are always sucessful, however after that blocks of writes fail in some multiple of 8 words. I.e, on the second pass I might see "1" on the first 16 words in memory then "0" for the next 8, then "1" for the next 8. | 21:59 |
| loxodes | If I read N words from different portion of memory in C in the firmware memory prior to writing a burst of words, the first N writes during a burst from the Migen module to SRAM work. (Where working is that I read back the expected value for that memory location from the firmware.) | 21:59 |
| loxodes | Do y'all have any ideas on what might be the source of this behavior? (Is there caching or buffering happening when writing to memory somewhere that might overflow but still pass back a high ACK over wishbone but discard a write attempt? Are long bursts of writes over wishbone not expected work?) | 21:59 |
| mithro | _florent_: It might also be worth mentioning that the most popular RISC-V core used with LiteX is not written in Migen but in-fact SpinalHDL | 22:59 |
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