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| lf | there is nmigen on the roudmap but is there anyone working on that atm? or am i missing something. | 16:37 |
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| ranzbak | Hi, I'm looking for the native interface documentation of the LiteDRAM IP, but I can't find it on Google. It would really help me if I know what signal does what, and if they are active high/low. | 18:07 |
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| zyp | ranzbak, I don't know if there's any documentation apart from the code itself, I'd probably start out by looking at how the existing frontends are using the native ports | 18:54 |
| zyp | at a glance it looks like the native interface is simply three streams, cmd stream takes address and whether it's a read or write, wdata stream takes the written data and a byte enable, rdata stream returns the read data | 18:58 |
| ranzbak | Okay thanks, and the user_clk is that the DDR speed clock or is it the interface clock with the MIG core? | 19:01 |
| ranzbak | @zyp I'll have a look at the frontend code indeed, If I have a half decent text file I'll create a pull request adding an md file to the doc directory, if that would help. | 19:04 |
| zyp | are you trying to use litedram standalone? | 19:08 |
| ranzbak | Yes, to connect it to a Minimig core. | 19:11 |
| zyp | looking at the generator, user_clk is the interface clock | 19:12 |
| ranzbak | Thanks :-) | 19:14 |
| ranzbak | Is the build tcl supposed to work with Vivado 2020.1 btw? | 19:34 |
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