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| atommann_ | Litex rocks! Linux boots successfully on our board (I name the board LogicField). | 09:41 |
| atommann_ | The memtest is not stable now, I reboot the board several times can boot Linux one time. | 09:42 |
| atommann_ | The frequency is 100MHz. Later I try lower frequency such as 75MHz. | 09:43 |
| atommann_ | I get Memtest OK every time at 75MHz. | 10:01 |
| atommann_ | I just test more, well not every time, but much better than before. Still need to learn more. | 10:08 |
| _florent_ | atommann_: nice, i could do a review of your Platform/Target if you share it | 10:53 |
| atommann_ | OK. Tonight I want to do more tests. | 11:18 |
| TMM | Yay, got the board. I'm just trying to see if everything works and I got a counter :) (small victories) I'm now trying this: https://github.com/antmicro/symbiflow-examples and it appears to maybe work, I have lxterm setup from litex but when I try any speed other than 115200 the serial line gets garbled. The linux-on-litex repository suggests 1e6 for --speed but that seems to not work there. Is that to do with the way symbiflow built the arty | 11:39 |
| TMM | verilog or am I missing some pieces? | 11:39 |
| tpb | Title: GitHub - antmicro/symbiflow-examples (at github.com) | 11:39 |
| TMM | at the current speed loading the linux image is taking a very, very long time | 11:39 |
| TMM | (but it is loading) | 11:39 |
| TMM | hmm, now I'm just seeing "Liftoff!" and not a lot else. The images that came with the demo didn't have a json file so took the one from the other repo. Maybe it's all in the wrong location in ram now | 11:51 |
| atommann_ | TMM, do you build everything in linux-on-litex-vexriscv folder with command like ./make.py --board=kc705 --build ? | 11:59 |
| atommann_ | Another command for building is: python3 litex-boards/litex_boards/targets/boardname.py --cpu-type vexriscv --build | 12:00 |
| atommann_ | And I found the output from these two methods are different. | 12:01 |
| atommann_ | I learned the 2nd method in a github issue. | 12:02 |
| TMM | I used the symbiflow Linux example, I didn't build the bits myself | 12:53 |
| TMM | I'll just follow the full instructions instead, see what that gives me | 12:53 |
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| _florent_ | TMM: sorry i haven't tested personally the symbiflow example so can't help, but following linux-on-litex-vexriscv repository for arty should work (but requires Vivado) | 13:17 |
| TMM | _florent_: is there a way to run linux-on-litex-vexrisc using symbiflow? litex supports it for the arty, right? | 13:19 |
| _florent_ | TMM: i think that's possible with the symbiflow tutorial, but haven't tested it. kgugala_ could probably provide more information on this | 13:20 |
| TMM | the symbiflow tutorial doesn't really use litex, it has verilog code that (from my understand of the flow as it is now, which definitely is... rudimentary) got generated by litex | 13:21 |
| somlo | _florent_: s/sdcard_pads/sdpads/ in https://github.com/enjoy-digital/litesdcard/blob/master/litesdcard/phy.py#L477 | 13:25 |
| tpb | Title: litesdcard/phy.py at master · enjoy-digital/litesdcard · GitHub (at github.com) | 13:25 |
| _florent_ | somlo: thanks, i'll fix it | 13:26 |
| _florent_ | somlo: i did some changes to the initialization (with the timeout you used, it was taking too long report a fail when the SDCard was not inserted), could you do some tests with the updated init? | 13:27 |
| somlo | build in progress, should have it ready in a few minutes | 13:28 |
| _florent_ | somlo: perfect, thanks | 13:30 |
| TMM | _florent_: what's the best way to learn how this all fits together? I found in litex how to tell it to use symbiflow but it appears that the linux-on-litex repo has some vivado command hardcoded in a file that says "# Autogenerated by LiteX / git: 51f2e6ce". So I assume there's some build step that happened on that repo? | 13:37 |
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| _florent_ | TMM: you can have a look at https://github.com/litex-hub/fpga_101 and the LiteX wiki (that is still in construction): https://github.com/enjoy-digital/litex/wiki | 13:39 |
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| tpb | Title: GitHub - litex-hub/fpga_101: FPGA 101 lessons/labs (at github.com) | 13:39 |
| _florent_ | But for Linux on LiteX-Vexriscv, only Vivado is officially supported on 7-Series/ devices. The Symbiflow team did an experimenation with the toolchain, but that's not user ready (at least not fully integrated in LiteX) | 13:42 |
| _florent_ | The only target that has Symbiflow support in LiteX is the Arty: https://github.com/enjoy-digital/litex/blob/master/litex/boards/targets/arty.py, but that's still experimental and has only be tested on the non-linux SoC | 13:43 |
| TMM | _florent_: I don't mind figuring out how all of this works, and see if I can get it to work at all. It seems like a good way to learn how all of the parts move together. I'm really not interested in using a non open source tool for any of my project. And I got an Arty :) | 13:43 |
| TMM | I don't need any of this to 'just work' but now I'm staring at a gigantic pile of software and hardware all of which I know nothing about :) | 13:44 |
| _florent_ | TMM: sure i understand, we would be interested in having your help/feedback improving this | 13:45 |
| _florent_ | I think a starting point for you would be to look at: https://github.com/enjoy-digital/litex/issues/554 | 13:45 |
| tpb | Title: improve Symbiflow/Arty support · Issue #554 · enjoy-digital/litex · GitHub (at github.com) | 13:45 |
| _florent_ | and try to build the Arty target with Symbiflow | 13:46 |
| _florent_ | to switch to the Linux SoC, you will first need to get the DDR3 working with symbiflow | 13:47 |
| _florent_ | i know this has already been validated, this is not integrated in the LiteX target, feel free to ask questions in the PR about this and why it hasn't been integrated in the initial PR | 13:49 |
| TMM | Alright, I'll first try to run the parts that are already supported and try to go from there | 13:49 |
| TMM | I should be able to build a non-linux soc with litex 'as is' right? | 13:49 |
| _florent_ | once you have DDR3 working with Symbiflow, getting the Linux-On-LiteX-Vexriscv SoC working will only be a matter of switching to the SoCLinux class | 13:50 |
| _florent_ | yes you should be able to build the Arty target with Symbiflow (adding --toolchain=symbiflow) | 13:51 |
| TMM | OK, I'll see how that's supposed to work then. From what I gathered so far is that I have to write a python script that defines what I want to build and then run that, I think? (I'm sorry I'm trying to find all of these parts and I'm probably asking kind of dumb questions but none of this seems to be for beginners :) I really appreciate your patience with me) | 13:52 |
| _florent_ | Yes, you describe your design in python with Migen/LiteX classes/modules, during the build, LiteX will convert the design to verilog and constraints files for the toolchain (basically the files that have been committed to the symbiflow example repository) and it will also run the toolchain for you to produce the bitstream that you will load in the FPGA. | 13:59 |
| somlo | _florent_: sdcardboot fails for me right now (nexys4ddr, rocket) | 14:05 |
| somlo | not sure whether it's the timeout or something else at this point | 14:06 |
| somlo | rebuilding with debug printf's to pinpoint where exactly it thinks it's failing | 14:10 |
| TMM | _florent_: so the boards/targets python scripts are sort of pre-defined sets of components to create an SoC from? | 14:11 |
| _florent_ | somlo: ok, don't spend to much time on this, i'll push some changes soon. | 14:11 |
| _florent_ | TMM: the board provide the definition of you hardware (IOS, interfaces, clocks, etc...) | 14:12 |
| _florent_ | TMM: sorry the platform file | 14:12 |
| _florent_ | the target is your design and LiteX provides default targets with a simple SoC (CPU + ROM + SRAM + SDRAM when available + Ethernet, etc...) that you can use as a basis to create something more complex | 14:13 |
| TMM | I'm trying to run './arty.py --build --toolchain=symbiflow' in the 'targets' directory now but symbiflow's synth fails. It does appear that the version of litex I have is older than master, and there's some differences for the symbiflow target as well. | 14:14 |
| TMM | ok, that's probably trying to build something with a dull dram controller etc so that's probably something that's also not supposed to work | 14:20 |
| TMM | or perhaps the default installation instructions give me too old a version of either litex or symbiflow, or both | 14:20 |
| somlo | TMM: IMHO, for a xilinx based board, it'd be worth building some vanilla litex design with *vivado* first, to smoothen the learning curve, before diving into figuring out the additional quirks of doing it with symbiflow | 14:20 |
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| TMM | somlo: if I really can't get anything to work at all I'll probably do that. I just don't want to give up straight away :) | 14:31 |
| somlo | _florent_: there are a lot of new `if (something != SD_OK) return 0;` in sdcard_init(), and printfs don't show a consistent one of them failing :( | 14:37 |
| somlo | sometimes it fails at sdcard_all_send_cid(), sometimes it's during sdcard_select_card(rca) -- it's not anything simple, so I'll just wait for your next update before testing again :) | 14:38 |
| _florent_ | somlo: ok, i also have issue with the recent changes on the way the clock is generated, i'm looking at this | 14:38 |
| _florent_ | somlo: could you try reverting this in SDPHYIOGen: https://github.com/enjoy-digital/litesdcard/commit/db607647d8fada2ecd6d827aaa12e2fb22ec5a33 | 14:39 |
| tpb | Title: phy/SDPHYIOGen: use SDROutput for clk. · enjoy-digital/litesdcard@db60764 · GitHub (at github.com) | 14:39 |
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| somlo | _florent_: the whole commit, or just the chunk in SDPHYIOGen? | 14:51 |
| _florent_ | somlo: just the change in SDPHYIOGen | 14:51 |
| somlo | ok, building... | 14:53 |
| somlo | _florent_: still fails with this patch on top of litesdcard: https://pastebin.com/77Z1txJv | 15:20 |
| tpb | Title: [Diff] diff --git a/litesdcard/phy.py b/litesdcard/phy.py index 0b94cb1..f4204ee 10064 - Pastebin.com (at pastebin.com) | 15:20 |
| _florent_ | somlo: ok thanks, i'm doing others changes on the clocking/reset and will tell ask you to test when done/committed | 15:46 |
| somlo | cool, sounds like a plan! | 15:49 |
| atommann_ | _florent_, Just emailed you, please have a look when you have time. Thank you. | 16:17 |
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| _florent_ | somlo-ci: could you trigger a build? :) | 18:04 |
| somlo | _florent_: building... | 18:15 |
| somlo | _florent_: sorry, still failing (not hanging at least, but falling through to netboot) | 18:58 |
| _florent_ | somlo: ok thanks. I still have some work to do on the write data path, once done i'll do more tests on various boards | 19:34 |
| keesj | I did not know the im-tomu usb core was rewritten in migen https://github.com/im-tomu/valentyusb/tree/master/valentyusb/usbcore/rx | 19:37 |
| tpb | Title: valentyusb/valentyusb/usbcore/rx at master · im-tomu/valentyusb · GitHub (at github.com) | 19:37 |
| somlo | _florent_: it's all good, thanks for making sdcard awesome! In the mean time, I'm looking into the nitty gritty details of Rocket's slave MMIO (DMA) port | 19:37 |
| somlo | we might need the wishbone UpConverter back, and maybe a wb-slave-to-axi-master conversion (to connect to the axi slave port) -- not sure what's already in there can work bi-directionally | 19:39 |
| somlo | maybe I'll use my vacation days to finally master migen FSMs (since it looks like I'm not going anywhere this summer) :D | 19:39 |
| somlo | _florent_: just for the record, right now this is where it fails: https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/liblitesdcard/sdcard.c#L475 | 19:51 |
| tpb | Title: litex/sdcard.c at master · enjoy-digital/litex · GitHub (at github.com) | 19:51 |
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