Monday, 2020-07-06

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xobsHey all, I'd like to announce the release of `wishbone-bridge` as a Rust crate. It's up at https://crates.io/crates/wishbone-bridge and current docs are at https://docs.rs/wishbone-bridge/1.0.0/wishbone_bridge/13:30
tpbTitle: wishbone_bridge - Rust (at docs.rs)13:30
xobsIt's the first release of the core that powers `wishbone-tool`, with the goal of making it easy to write thin wrappers around programs that interact with a device under test.13:31
xobsIt's still all located within `https://github.com/litex-hub/wishbone-utils/`, and it's the same backend bridge library that's still being used by `wishbone-tool`.13:32
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TMMThis is probably a silly question but is there a programming limit on FPGAs like on flash?15:54
daveshahFlash FPGAs, yes15:55
daveshahSRAM FPGAs, no15:55
TMMOh, some FPGAs have flash on the board itself?15:55
TMMor on the chip itself I guess15:56
daveshahSome FPGAs have flash on die15:56
daveshahMachXO and some microsemi ones15:56
TMMAh, and others load it dynamically on 'boot'?15:56
daveshahEven MachXO does as the FPGA array is still SRAM based15:56
daveshahIt just has microcontroller style built in flash that it loads from by default15:57
daveshahSome FPGAs, Microsemi in particular, do have genuine flash based arrays still aiui15:57
TMMAlright, so if I wanted to design a board with one 'empty' fpga that can be programmed from the OS on it I'd want one that ram based and load the code from the main cpu?15:57
daveshahYes15:58
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atommannHi _florent_, The reset button of KC705 is active high. My board's reset signal is active low. How can I change this logic?16:25
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_florent_atommann: you can invert it as done on Arty for example: https://github.com/enjoy-digital/litex/blob/master/litex/boards/targets/arty.py#L4117:06
tpbTitle: litex/arty.py at master · enjoy-digital/litex · GitHub (at github.com)17:07
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atommannHey, the RESET logic works fine now!17:34
atommannThank you _florent_.17:34
atommannMemtest still fail. Tomorrow I read more issues to see the workaround.17:35
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