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| futarisIRCcloud | Great discussion on how to renumerate LiteX SoC over PCIe. Android USB Accessory is another example of how one protocol is enumerating over another. I guess Linux USB over IP is another. | 00:21 |
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| atommann | Good morning. | 02:27 |
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| TMM | _florent_: well, I bought an Arty A7-35T! :D | 10:24 |
| acathla | TMM, congratulations! But that was the easy part :) | 10:54 |
| trabucayre | I regret lack of USB port on this board | 11:30 |
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| zyp | _florent_, I've been going through litepcie to figure out how stuff fits together, got a couple of questions if you don't mind | 11:50 |
| zyp | I see S7PCIEPHY has a bar0_size argument, but as far as I can see, BAR0 is hardcoded to 1MB in the .xci -- what is then the point of the argument? | 11:51 |
| zyp | also, apart from changing the .xci, what would be required to support more than one BAR? | 11:52 |
| _florent_ | zyp: we were previously integrating the pre-generated verilog and passing the bar0 size argument to them, but i changed this to use the .xci and generate the verilog when building the project | 12:06 |
| _florent_ | bar0 size is parameter is still used for address masking on the wishbone bridge IIRC | 12:06 |
| _florent_ | i don't think supporting multiple bar0 would be too complicated, we would need to get the bar information from the incoming TLP | 12:08 |
| TMM | acathla: sure, required but not sufficient :) Making a choice what direction to go to though! | 12:14 |
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