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| somlo | _florent_: good morning! (I think :) ) | 02:06 |
|---|---|---|
| somlo | just dumped a whole bunch of stuff into github, getting readyo to go to sleep over here... | 02:07 |
| somlo | *ready | 02:07 |
| somlo | but long story short, I got sdcard to properly pass testing on rocket (with either 8 or 32bit simple CSRs) | 02:08 |
| benh | somlo: hey | 02:22 |
| benh | I very much disagree with your "fix" for the CSRs, this brings back a breakage I fixed actually :) | 02:23 |
| benh | _florent_ somlo: see my comment on the github issue. I can try to investigate why it broke on Mor1kx but making the access size match the actual CSR size was done on purpose, otherwise we end up generating multi-beat transfers on every CSR access | 02:24 |
| benh | when the unsigned long is wider than the CSR size | 02:24 |
| benh | my patch *should* have taken the alignment into account via CSR_OFFSET_BYTES and it works on microwatt which has a 64-bit bus and 32-bit CSRs | 02:24 |
| benh | so I don't know why Mor1kx broke at this point, if you have info, please share, otherwise I'll try to investigate this week-end | 02:25 |
| benh | but I very very much disagree with your "fix" | 02:25 |
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| _florent_ | somlo: good for the sdcard, i will look at your changes | 09:50 |
| _florent_ | somlo, benh: we could discuss the right solution for the CSR fix in the issue and should also probably limit the supported CSR configurations to simplify things | 09:52 |
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| benh | _florent_: I agree, there is no point in supporting every combination under the sun, it's just a pain to maintain & test long run | 10:15 |
| benh | _florent_: and if we support them today & people use them it gets harder to get rid of | 10:15 |
| benh | _florent_: so yes, I wholeheartedly agree :) 32-bit and 8-bit CSR both on a 32-bit wishbone makes sense | 10:16 |
| benh | not sure if there's real advantage to the 8-bit case but we can keep it around if it really saves resources (it does add muxes and uses less registers, I tend to find that we run out of muxes/timing faster than we run out of registers but that's my use cases) | 10:16 |
| benh | if 64-bit systems always have a proper down-converter to 32-bit then alignment can be removed | 10:17 |
| benh | and such systems can just use normal 32-bit with 32-bit alignment | 10:17 |
| benh | we still need to decide on endian :) but that's less urgent | 10:18 |
| _florent_ | yes this seems fine and easier to support in the long term | 10:18 |
| benh | somlo: opinions ? :) | 10:19 |
| benh | _florent_: if we go down that path, we could simplify hw/common.h a lot too | 10:19 |
| benh | we can make csr_*simple just open-code the 4 read/write for the 8-bit case and make everything else operate on 32-bit quantities | 10:21 |
| somlo | _florent_, benh: I honestly wish the CSR bus had some concept of strobes :) | 10:29 |
| somlo | because that's the main reason we have to have 64bit CSR alignment right now | 10:29 |
| somlo | i.e., the 64bit CPU makes 64-bit accesses for *everything* (even an 8bit read/write), which then gets translated into two 32-bit accesses by the wishbone down-shifter, which then touches two adjacent 32-bit CSRs (if they're not 64-bit aligned), regardless of whether one half of the original 64-bit request is completely strobed out | 10:30 |
| _florent_ | somlo: we could handle the strobes in the Wishbone2CSR converter | 10:30 |
| _florent_ | somlo: ie, if the strobes are not set for the the 32 LSB or MSB, we could just avoid the access on the CSR bus for this | 10:31 |
| somlo | right, and then we could get rid of 64-bit alignment. I'm just saying, with the way things are right now, the MMIO (simple) accessors are what they need to be. They're wrong on some "ideal" hardware we don't (yet) have :D | 10:31 |
| _florent_ | somlo: ok, so we could work on this together | 10:33 |
| somlo | and I'll take a pass at fixing the "buffer" accessors for non-multiple cases, unless whatever we're about to do changes *that*, in which case I'd wait until the dust settles :D | 10:33 |
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| benh | wait... | 11:13 |
| benh | why would it do that ? | 11:13 |
| benh | I mean, why would the 64->32 downconverter generate cycles for the lanes that have no byte enable ? | 11:13 |
| benh | mine doesn't :-) | 11:13 |
| benh | (the one I have in microwatt) | 11:13 |
| benh | and yes, the Wishbone2CSR converter should definitely check the enables | 11:14 |
| benh | for 32-bit and 8-bit | 11:14 |
| benh | _florent_: ok so I see two issues indeed with the approach I want for the accessors | 11:23 |
| benh | _florent_: indeed it looks like the wishbone downconverter will turn any access from a 64-bit master into 2x32-bit access downstream even if sel's are all 0 | 11:23 |
| benh | that should/could probably be optimized :) | 11:24 |
| benh | (unless I'm misreading the migen) | 11:24 |
| benh | _florent_: and yes Wishbone2CSR should probably check that relevant sel bits are set for the CSR size | 11:24 |
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| _florent_ | somlo: could you do some tests with Rocket, 32-bit CSR alignment and https://github.com/enjoy-digital/litex/commit/759367752caf21475b57d468a442635a87ac273b? | 13:23 |
| tpb | Title: wishbone/wishbone2csr: use wishbone.sel on CSR write. · enjoy-digital/litex@7593677 · GitHub (at github.com) | 13:23 |
| _florent_ | to use 32-bit CSR alignment, you can just comment: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc.py#L794 | 13:24 |
| tpb | Title: litex/soc.py at master · enjoy-digital/litex · GitHub (at github.com) | 13:24 |
| benh | _florent_: if we start making the main wishbone 64-bit, we'll have more 64->32 downconverters for random IO parts (not a bad idea for utilization anyway) | 13:24 |
| benh | _florent_: might be worth looking at avoiding the downstream phases for unused sels | 13:24 |
| benh | _florent_: in microwatt it's easy bcs the downconverter is hard wired for 64-32 :) | 13:24 |
| benh | _florent_: the general case is harder but we could special case the "half size" case in the generator | 13:25 |
| benh | _florent_: I basically have two signals "have_top" and "have_bottom" and define the next state based on them with a state for each half | 13:25 |
| somlo | _florent_: seems to work in sim with rocket and 32-bit csr data width; I'll run some more tests, and try on the nexys4ddr after that | 14:28 |
| somlo | then I'll pretty much have to overhaul the 64-bit linux drivers in litex-hub/linux :) | 14:29 |
| somlo | but writing to the scratch register no longer causes the SoC to reset (because of the preceding reset register contained within the same 64-bit aligned pair :) | 14:29 |
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| somlo | 32-bit alignment appears to work on nexys4ddr with rocket and the updated sdcard code from PR 547 | 15:12 |
| somlo | _florent_: are you planning to officially comment out https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc.py#L794 upstream? | 15:13 |
| tpb | Title: litex/soc.py at master · enjoy-digital/litex · GitHub (at github.com) | 15:13 |
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| _florent_ | somlo: thanks for the test, yes i was planning to remove the CSR re-alignment on the CPU data width if it was working without for you | 19:59 |
| _florent_ | somlo: maybe we should also remove 64-bit CSR alignment at the same time | 20:01 |
| _florent_ | benh: i agree we should avoid downstream access if sel is not set, i will look at implementing it. Here i just wanted to see if we could avoid the 64-bit CSR alignment support | 20:03 |
| somlo | _florent_: I think I'm ok with removing 64bit alignment altogether | 21:57 |
| somlo | I assume the linux drivers will be more or less the same in that case for both vexriscv and rocket | 21:58 |
| somlo | but I can check (and clean things up if needed) | 21:58 |
| somlo | I have 15 days of time off and nowhere to go (my flight to Budapest just got canceled, so no vacation this summer for the Somlos :( | 21:59 |
| somlo | on the bright side, I can spend some fun time with LiteX now that $DAYJOB won't pay for it anymore :D | 21:59 |
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