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| tmbinc | Is there something existing that implements a wishbone slave on the host side in verilator for co-simulation? | 19:29 |
| dkozel | gr-verilog has a C++ streaming interface to AXI in Verilator, probably pretty easy to adapt to wishbone | 19:45 |
| _florent_ | tmbinc: IIRC Antmicro did some work on that, but i'm not able to find the link | 19:54 |
| _florent_ | tmbinc: not sure it was that, but could be useful: | 19:55 |
| _florent_ | https://antmicro.com/blog/2019/09/renode-verilator-hdl-co-simulation/ | 19:55 |
| tpb | Title: Antmicro · Co-simulating HDL models in Renode with Verilator (at antmicro.com) | 19:55 |
| _florent_ | https://antmicro.com/blog/2019/06/verilog-with-cocotb-and-verilator/ | 19:56 |
| tpb | Title: Antmicro · Open source Verilog simulation with Cocotb and Verilator (at antmicro.com) | 19:56 |
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| benh | _florent_: I noticed litedram on my arty spews a couple of DRC warnings in Vivado about IBUFDS having no loads, is htat expected ? | 22:37 |
| benh | toplevel_drc_opted.rpt:Input buffer has_dram.dram/litedram/IOBUFDS/IBUFDS (in has_dram.dram/litedram/IOBUFDS macro) has no loads. It is recommended to have an input buffer drive an internal load. | 22:37 |
| benh | (and another one about IOBUFDS_1 | 22:38 |
| benh | _florent_: also something about all outputs of IDELAYTRL being unconnected, logic might be removed | 22:42 |
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