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| benh | _florent_: not quite working yet :-) See emails | 02:04 |
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| benh | _florent_: so your latest change is triggering its own slew of problems | 10:06 |
| benh | _florent_: as I wrote in my response, the values in csr.h are wrong ... I tried using my own CSR accessors via CSR_ACCESSORS_DEFINED | 10:07 |
| benh | _florent_: but that's broken by all the "new" accessors in common.h | 10:07 |
| benh | things like csr_rd_buf_uint8 | 10:07 |
| benh | there is no extern definition of them in csr.h | 10:07 |
| benh | and they are not defined at all by common.h when CSR_ACCESSORS_DEFINED is set | 10:08 |
| benh | so essentially, whatever CSR_ACCESSORS_DEFINED might have once been intended for, it's broken | 10:08 |
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| benh | that said, those "new" accessors are also broken in different ways (my earlier discussion on this a few days ago) since they don't do memory barriers or similar | 10:09 |
| benh | it's particularly broken in that the new accessors will always do 64-bit accesses | 10:10 |
| benh | on a 64-bit platform | 10:10 |
| benh | so they will always 2 consecutive accesses to a 32-bit downconverted wb/csr bus | 10:11 |
| benh | which is not ideal, or even broken if you don't also set csr_alignment to 64-bit | 10:11 |
| benh | trying to fix that stuff but I'll need help testing the changes | 10:27 |
| benh | somlo: ping | 10:35 |
| benh | somlo: is it me mis-reading the code or are the "new" CSR accessors such as _csr_rd assume that CSRs are spaced "unsigned long" appart ? | 10:37 |
| benh | somlo: ie, 64-bit appart on a 64-bit system, and 32-bit appart on a 32-bit system | 10:37 |
| benh | somlo: due to how you just index a unsigned long* to increment addresses | 10:37 |
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| benh | somlo: shouldn't it instead be incremented by CONFIG_CSR_ALIGNMENT/8 bytes ? | 10:38 |
| benh | somlo: for example on microwatt I can have a setup such that CSRs are 32-bit appart on a 64-bit system | 10:38 |
| benh | (I don't have to ... but I can :-) | 10:38 |
| benh | also you can have processors that can run either 32-bit or 64-bit code... | 10:39 |
| benh | somlo: _florent_ : If you have a chance, can you take aa peek at https://pastebin.com/jZNstq58 | 10:50 |
| tpb | Title: [C] --- a/litex/soc/software/include/hw/common.h +++ b/litex/soc/software/include/h - Pastebin.com (at pastebin.com) | 10:50 |
| benh | mostly untested (other than my sdram init builds :-) | 10:50 |
| benh | but this allows to override csr_{read,write}_simple and have everything else built on top of them | 10:50 |
| benh | it shoudl also fix cases where CONFIG_CSR_ALIGNMENT/8 != sizeof(unsigned long) | 10:51 |
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| somlo | benh: CONFIG_CSR_ALIGNMENT/8 should always equal sizeof(unsigned long) | 10:57 |
| benh | somlo: who says ? | 10:59 |
| benh | ie, why ? :-) | 10:59 |
| somlo | https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/include/hw/common.h#L30 | 10:59 |
| tpb | Title: litex/common.h at master · enjoy-digital/litex · GitHub (at github.com) | 10:59 |
| benh | anyways, see the patch I posted, tell me what you think | 10:59 |
| benh | _florent_: this change of yours looks broken in litedram: if cpu_type is None: | 10:59 |
| benh | wb_bus = wishbone.Interface(self.bus.address_width) | 10:59 |
| benh | ie, you removed adr_width= so it's now setting the *data* width | 11:00 |
| somlo | benh: because it's always been 32 until the first 64bit CPU was added to litex (rocket), and I had to make it 64 on 64 to get it to work properly :) | 11:01 |
| benh | somlo: well, that's my whole point :-) | 11:01 |
| benh | somlo: I don't like how you wrote that code | 11:01 |
| benh | and it's a mistake to make that assumption that CSRs are unsigned long spaced | 11:01 |
| benh | and it's a bigger mistake to dereference an unsigned long to access them for a number of reasons | 11:02 |
| benh | one big one being that you can't just "access" IOs like that on most CPU architectures, you need things like memory barriers etc.. | 11:02 |
| somlo | but right now they *are* -- not opposed to expressing that better, or fixing the underlying hardware so they don't *have* to be, but right now them's the breaks :) | 11:02 |
| benh | but you can have a 32-bit wishbone bridged | 11:02 |
| benh | on your 64-bit main bus | 11:02 |
| benh | which means now each of your CSR access turns into *2* accesses... pointlessly | 11:03 |
| benh | somlo: well, my point is that code is broken :-) Anyway, see the pastebin link I pasted above | 11:03 |
| benh | it's a quick attempt at fixing this and re-viving the ability to provide custom accessors with CSR_ACCESSORS_DEFINED which all those new things broke | 11:03 |
| somlo | I remember something about the CSR bus lacking a byte select signal, and adjacent registers being inadvertently "touched" without the software meaning to, on 64bit | 11:04 |
| benh | it's mostly untested for now as I'm working through other changes but please provide feedback | 11:04 |
| benh | somlo: well, if they are 64-bit appart, that hopefully won't happen but you might end up still doing weird things | 11:04 |
| benh | like writing the same reg twice | 11:04 |
| benh | again, *hopefully* my changes should fix all that | 11:05 |
| benh | the basic idea is that all the new fangled accessors are expressed on *top* of csr_{read,write}_simple and don't do poitner magic, but instead calculate the proper offset between registers | 11:05 |
| benh | and the csr_{read,write}_simple implementation is responsible for using the right access size | 11:05 |
| benh | I haven't fixed the latter in the general case yet | 11:06 |
| benh | only for me as I provide custom ones (with the proper memory barrier) | 11:06 |
| benh | but I'll do that next | 11:06 |
| somlo | I'm ok with rewriting a[i] as csr_*_simple(a) if that's the question :) | 11:06 |
| benh | and taking out the pointer arithmetic | 11:06 |
| benh | next (which I haven't done yet) is I'll make the default implementation of csr_*_simple use a csr_type * where csr_type is defined to the right uint64_t/uint32_t/uint8_t | 11:07 |
| benh | however, anything with an out of order memory model will probably need to provide its own implementation using appropriate IO accessors | 11:07 |
| benh | I'll look into that next, it will be needed for powerpc at least | 11:08 |
| benh | _florent_: I'm having some trouble figuring out how the CSR address decoding is done :-) It looks like the generated verilogg checks address bits 0 and 1 on 32-bit CSRs with 64-bit aliggnment | 11:13 |
| benh | _florent_: so I have to pass it something padded with "000" on the right | 11:13 |
| benh | somlo: generally LiteX needs proper IO accessors | 11:30 |
| benh | provided by the CPU implementation/wrapper | 11:36 |
| somlo | benh: if by that you mean `csr_[read|write]_simple()`, I agree. But I'd rather keep the higher-level (compound) register code common | 11:48 |
| benh | somlo: agreed, which is why I would like to build it on top of the simple ones | 11:51 |
| benh | somlo: https://github.com/ozbenh/litex/commits/csr-access-rework | 11:54 |
| tpb | Title: Commits · ozbenh/litex · GitHub (at github.com) | 11:54 |
| benh | somlo: let me know what you think please :-) | 11:54 |
| benh | somlo: I'll try to test it a bit in the meantime | 11:54 |
| somlo | benh: tbh, I used a[i] mostly because it helped me keep track of what's going on. But now that it's moe or less debugged and seems to work, I'm totally ok with factoring out the simple accesses as standalone functions | 11:58 |
| somlo | de002fe does that, as far as I can tell | 11:58 |
| somlo | I can try to test it later today, too, see what happens | 11:59 |
| benh | somlo: cool, thanks ! | 12:01 |
| benh | somlo: if you're happy with it I'll send _florent_ a PR | 12:03 |
| somlo | well, I tried building it, but there's syntax errors (token "=" is not valid in preprocessor expressions) :) | 12:03 |
| somlo | you wanna fix it and I can try again, or should I switch that to "==" locally ? | 12:03 |
| benh | somlo: ah I have my own CSR defs .. so I might have mangled that | 12:03 |
| benh | somlo: either, fixing it now | 12:04 |
| benh | that's the doom of constantly switching between programmingg languages :-) | 12:04 |
| benh | pushed | 12:05 |
| somlo | building now (for the trellisboard, with gateware and all, so it'll be 20-30 minutes) | 12:06 |
| benh | somlo: ok, thanks ! | 12:07 |
| benh | at some point I'll try to figure out how to add a cpu.h include that's provided by the cpu definition | 12:07 |
| benh | we''ll need things like proper IO accessors and memory barriers for DMA etc... | 12:07 |
| benh | that is then included by hw/common.h | 12:08 |
| benh | that will esp. matter when Dolu has SMP going as memory barriers, locks etc... are going to be a must have | 12:08 |
| benh | and those are at least architecture specific | 12:08 |
| benh | unless we entirely rely on the new fangled C primitives but ... | 12:09 |
| somlo | like the equivalent of `[read|write][l|q]()` in linux | 12:09 |
| benh | yup | 12:10 |
| benh | and memcpy_to/from_IO for ethernet | 12:10 |
| benh | and smp_mb/rmb/wmb, spinlocks, etc... | 12:10 |
| benh | for SMP VexRiscV | 12:11 |
| benh | etc... | 12:11 |
| somlo | Rocket could also be SMP, on larger FPGAs (I can barely fit a single core on ecp5, so it's never been a direct concern :) | 12:12 |
| benh | yeah a lot of these things aren't a concern ... yet :) | 12:13 |
| benh | but we fix microwatt in an Arty 35T today.. we could fit 2 in a 100T ;) | 12:14 |
| Dolu | benh: 2 SMP linux ready cores in 100T ? | 12:18 |
| Dolu | benh: about the smp stuff hw/common.h, you talk about its integration into the litex bios ? | 12:42 |
| _florent_ | benh: sorry, i wasn't on irc | 12:47 |
| somlo | benh: c9fb9cd `Reviewed-by: Gabriel Somlo <[email protected]>` fwiw (no mailing list to do this over) :) | 12:54 |
| zyp | somlo, fit on a -85, or smaller? | 12:55 |
| somlo | zyp: a linux-capable (though FPU-less) 64bit rocket + litex SoC utilizes cca. 60% of the -85 on a trellisboard, at the moment | 12:56 |
| somlo | a FPU-enabled single-core 64bit rocket will *not* fit on the -85 | 12:57 |
| zyp | I see | 12:57 |
| zyp | how does the ecp5 size figures compare to the artix-7 ones? is there a rough factor for comparisons? | 12:59 |
| somlo | zyp: the fpu-less single-core 64bit rocket *sometimes* fits on a -45 (on the ecp5 versa 5g). Utilization dances around the 100% logic block mark, and sometimes, when the stars align, you get 99% fromthe placer and routing can proceed | 12:59 |
| somlo | zyp: I think that's more of a daveshah question; I know I can do a fpu-enabled single-core rocket on the nexys4ddr (artix-7-100) | 13:00 |
| somlo | (with vivado, so not exactly apples-to-apples) | 13:01 |
| zyp | also, how far are we from being able to do a full artix-7 flow with open tools? | 13:02 |
| zyp | (somebody stop me if I'm asking too many stupid and/or offtopic questions) | 13:03 |
| daveshah | nextpnr for xilinx is probably a year away from being something I would actually recommend end users to use | 13:04 |
| daveshah | idk about vpr | 13:04 |
| zyp | what's the current state of nextpnr for xilinx? working but for a subset of features? | 13:06 |
| benh | somlo: thanks | 13:07 |
| benh | somlo: I'll send a PR | 13:07 |
| benh | Dolu: among others yes | 13:07 |
| sorear | given that riscv32 is probably never going to be well supported by binary distros, a more resource-efficient riscv64 is something I would like to see | 13:07 |
| daveshah | zyp: yes, roughly | 13:08 |
| zyp | daveshah, does a full nextpnr flow rely on any non-free bits at the moment, or is it possible to go all the way from verilog to a bitstream? | 13:11 |
| daveshah | You can go all the way to a bitstream with prjxray | 13:12 |
| zyp | nice | 13:14 |
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| Dolu | benh: So, basicaly, the integration which was done for VexRiscv SMP into litex bios is the following : https://github.com/enjoy-digital/litex_vexriscv_smp/tree/master/vexriscv_smp | 13:42 |
| tpb | Title: litex_vexriscv_smp/vexriscv_smp at master · enjoy-digital/litex_vexriscv_smp · GitHub (at github.com) | 13:42 |
| Dolu | Only hart 0 get through crt0 to the bios code, the others will wait, and only be unlocked at the last moment before jumping into the payload (opensbi / linux) | 13:43 |
| Dolu | So, nearly nothing SMP at the litex bios level | 13:44 |
| benh | Dolu: ok, so yes, system.h isn't a bad place for that I suppose though it should probably be cpu.h | 13:46 |
| benh | for core specific bits | 13:46 |
| benh | Dolu: we would want a way to put MMIO accessors in there as well... I can propose something later, it's past bed time here :) | 13:46 |
| benh | _florent_: btw, microwatt will probably break on/off with LiteX ... I'll fix things up soon. The way we feed interrupts to the core for example is probably due to change | 13:49 |
| Dolu | benh: Ahh right, MMIO accessors should be added | 13:56 |
| Dolu | sorear: unfortunatly :(, i have no good idea how much RV64 would inflate VexRiscv | 13:57 |
| benh | microwatt with MMU takes about half an Arty 35T | 13:58 |
| benh | no FPU and no SIMD | 13:58 |
| benh | but it boots a hacked up linux | 13:58 |
| benh | it also could use bigger caches/TLBs and generally be faster, it still somewhat sucks ;-) | 13:59 |
| benh | VexRiscV starts with a much slimmer base line, it should be possible to keep it below that, again without FP and SIMD | 13:59 |
| sorear | possibly interesting experiment: add FP registers and loads/stores so that setjmp/longjmp and context switches don't trap, how much that makes things faster at what cost | 14:01 |
| benh | sorear: pretty much waht Paul is doing right now :-) | 14:14 |
| benh | add the basic regs and load/stores and SW emulate the rest | 14:15 |
| benh | maybe with a handful of "assist" instructions | 14:15 |
| sorear | (Paul?) | 14:15 |
| benh | the load/stores do require a bit of fiddling for single/double conversion etc. | 14:15 |
| benh | Paul Mackerras | 14:15 |
| benh | (on Microwatt that is) | 14:15 |
| sorear | ah | 14:15 |
| sorear | riscv is easier, there's no single/double conversion :) | 14:16 |
| benh | hehe | 14:16 |
| benh | I am not familiar with riscv FPU... double only ? | 14:16 |
| sorear | this is my one contribution to the riscv base spec | 14:16 |
| benh | on powerpc, it's always stored as a double in the register, so load/store single have to convert | 14:16 |
| sorear | the registers are double-sized, loading a single value and then storing it as double pads it on the left with 32 1s | 14:16 |
| benh | ok | 14:17 |
| sorear | so it becomes a DP NaN | 14:17 |
| benh | so the actual arithmetic ops operate on what ? | 14:18 |
| sorear | the actual arithmetic ops are all tagged with a size and there's an explicit "double/single conversion with register src and dest" instruction | 14:18 |
| sorear | mixing sizes on a register without conversion will not do anything useful | 14:19 |
| benh | I see.. doesn't that make the FPU more complex ? | 14:19 |
| sorear | it's supported exactly to the extent to allow registers containing single to be saved and restored by generic code | 14:19 |
| benh | powerpc always has doubles in the registers and all arith. ops are double | 14:19 |
| benh | single is only an artifact of load/store conv. | 14:19 |
| benh | I suppose it's just a few more muxes in the FPU to select how many bits of mantissa and exponent you use based on the tag | 14:21 |
| sorear | ugh, FLT_EVAL_METHOD makes me sad | 14:21 |
| benh | but that adds to the critical timing path, doesn't it ? | 14:21 |
| sorear | I forget exactly what we put where, but Rocket uses an internal 65-bit float format with no subnormals and all of the annoying timing stuff happens on loads/stores only | 14:23 |
| sorear | doing single math in real single precision is important, it means fp behavior doesn't silently change between -O0 and -O1 | 14:24 |
| sorear | i686 gets this catestrophically wrong (all operations are *long double* unless spilled to memory), it sounds like ppc at least does double ops in intended precision | 14:25 |
| benh | yup | 14:26 |
| benh | allright, I do need to call it a day, it's already tomorrow here :-) | 14:27 |
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| CarlFK | xobs: bunnie: netv2 in a pc's pci slot - do I need to give it 12v on the barrel connector? | 19:26 |
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| kgugala | CarlFK: you can power it via pcie connector | 19:55 |
| CarlFK | kgugala: good. installing vivado now.. I need that right ? | 20:03 |
| kgugala | yep | 20:04 |
| kgugala | CarlFK: do you have a100t or a50t version of netv2? | 20:05 |
| CarlFK | both | 20:05 |
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| CarlFK | Vivado HLx 2019.2: All OS installer Single-File Download (TAR/GZIP - 26.55 GB) *surprised face* | 20:15 |
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| CarlFK | INFO : Installation completed successfully. | 20:36 |
| CarlFK | that' wasn't too bad. | 20:36 |
| CarlFK | kgugala: juser@cnt4:~/tv/netv2$ make gateware/target | 20:38 |
| CarlFK | make: *** No rule to make target 'gateware/target'. Stop. | 20:38 |
| CarlFK | kgugala: "4. Go back to netv2 directory and build the bitstream:" | 20:40 |
| kgugala | CarlFK you need to select the target e.g gateware/build or gateware/load (or clean) | 20:40 |
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| kgugala | or simply run make build - this should build all | 20:41 |
| CarlFK | there's no makefile 'here' | 20:41 |
| CarlFK | and i have a feeling there is some other netv2 dir I should be in | 20:42 |
| CarlFK | kgugala: nothing told me to git clone https://github.com/antmicro/netv2 | 20:44 |
| tpb | Title: GitHub - antmicro/netv2: NeTV2 SoC based on LiteX (at github.com) | 20:44 |
| CarlFK | I bet that's the netv2 dir I'm spozed to be in | 20:44 |
| kgugala | yep | 20:44 |
| kgugala | the repo where the readme is | 20:45 |
| CarlFK | kgugala: guessing I need to apt install something? OSError: Unable to find any of the cross compilation toolchains: - riscv64-unknown-elf ... | 21:04 |
| kgugala | yes you need RISC-V toolchain to build Litex bios | 21:05 |
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| kgugala | you can grab it from https://www.sifive.com/boards | 21:06 |
| tpb | Title: Boards & Software - SiFive (at www.sifive.com) | 21:06 |
| kgugala | Prebuilt RISC‑V | 21:07 |
| kgugala | GCC Toolchain | 21:07 |
| kgugala | section | 21:07 |
| CarlFK | kgugala: why does it say "unknown" in riscv64-unknown-elf ? | 21:31 |
| CarlFK | I'm guessing an env var needs to be set | 21:31 |
| tumbleweed | naah, that's just a standard gnu triplet | 21:58 |
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| CarlFK | tumbleweed: wut? | 22:04 |
| CarlFK | http://paste.ubuntu.com/p/2QQSxq66xK/ make build ... OSError: Unable to find any of the cross compilation toolchains: - riscv64-unknown-elf | 22:05 |
| tpb | Title: Ubuntu Pastebin (at paste.ubuntu.com) | 22:05 |
| tumbleweed | CarlFK: I mean the unknown there doesn't sonud too worrying | 22:06 |
| tumbleweed | the problem is that it can't find riscv64-unknown-elf | 22:07 |
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| CarlFK | tumbleweed: know if it is packaged? | 22:16 |
| CarlFK | https://github.com/riscv/riscv-gnu-toolchain#installation-linux | 22:16 |
| tpb | Title: GitHub - riscv/riscv-gnu-toolchain: GNU toolchain for RISC-V, including GCC (at github.com) | 22:16 |
| CarlFK | im compiling a compiler..it gving me gentoo flashbacks | 22:17 |
| daveshah | You can download it from https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-ubuntu14.tar.gz | 22:19 |
| daveshah | You don't need to build it from scratch | 22:20 |
| daveshah | (despite the ubuntu14 it seems to run fine on any linux) | 22:20 |
| CarlFK | application-specific initialization failed: couldn't load file "librdi_commontasks.so": libtinfo.so.5: cannot open shared object file: No such file or directory | 22:35 |
| CarlFK | but it is stil doing something | 22:35 |
| CarlFK | maybe not. cpus are all idle | 22:35 |
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| tumbleweed | CarlFK: install libtinfo5 | 23:04 |
| tumbleweed | (or go back to compiling compilers | 23:04 |
| tumbleweed | or install gcc-riscv64-unknown-elf - yes we do have a packaged cross-compiler | 23:05 |
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