Tuesday, 2020-05-12

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futarisIRCcloudhttps://twitter.com/janmarjanovic/status/1259529253126897666?s=1904:16
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benh_florent_: a couple of PR should be in your inbox (litex and litedram)12:02
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benh_florent_: the cpu_none tests in Travis failed, not sure what's up there, I have never used the test stuff yet12:35
_florent_benh: thanks for the PRs, i'll look at the tests while reviewing/merging12:38
benh_florent_: can I run those tests locally ?12:39
benhok thanks12:39
_florent_to run them locally: python3 setup.py test12:39
benhok, time for bed but if you don't get to sort it out by my tomorrow, I'll have a look, thanks12:42
_florent_i'm probably going to have a look at it now, have a good night :)12:43
shuffle2i have LiteEthPHYRGMII and LiteEthUDPIPCore with default dw=8, and done eth_core.udp.crossbar.get_port with dw=1612:45
shuffle2still having some misunderstanding of how stream is supposed to work, or something12:46
shuffle2e.g. on the rx path, if i send udp packet with data length 12, i would expect to see 6*2bytes of data12:46
shuffle2instead i see 9 pulses of valid from the converter...seems padded with zeros at the end?12:47
shuffle2even tho the depacketizer has latched correct length value12:47
shuffle2wireshark on the sending pc doesn't show the sender has added any padding, the stream should end after 12 bytes of data12:49
_florent_there is a minimum frame size with Ethernet, it's possible the hardware of your network card is inserting padding12:50
_florent_maybe you should try with a longer payload to see if you have the same behavior12:51
shuffle2_florent_: ah heh, that does seem to be what's happening :)12:54
shuffle2imo i/o from the "udp" level of liteeth should account for this tho?12:55
shuffle2i saw before liteeth mac layer inserts padding, too bad inverse can't be done in mac for rx12:57
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_florent_we could try to improve this, even if it's not possible at the MAC level, we could make sure the padding is removed at the UDP level13:05
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rw1nklerHey, is it possible to use multiple instances of serial2console in LiteX simulation? Currently, it gives me segmentation fault. I'm trying to simulate two UARTs20:48
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